OvmfPkg/PlatformPei: detect SMRAM at default SMBASE (for real)

[mirror_edk2.git] / OvmfPkg / PlatformPei / MemDetect.c

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 8fdc9c2ed7c9676163e5a3afa1518a0a15ddeaba..47dc9c543719a0f55c4279140d23a8d5822b57f2 100644 (file)
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -103,6 +103,22 @@ Q35SmramAtDefaultSmbaseInitialization (
   ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
 \r
   mQ35SmramAtDefaultSmbase = FALSE;\r
+  if (FeaturePcdGet (PcdCsmEnable)) {\r
+    DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE not checked due to CSM\n",\r
+      __FUNCTION__));\r
+  } else {\r
+    UINTN CtlReg;\r
+    UINT8 CtlRegVal;\r
+\r
+    CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);\r
+    PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);\r
+    CtlRegVal = PciRead8 (CtlReg);\r
+    mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r
+                                         MCH_DEFAULT_SMBASE_IN_RAM);\r
+    DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE %a\n", __FUNCTION__,\r
+      mQ35SmramAtDefaultSmbase ? "found" : "not found"));\r
+  }\r
+\r
   PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase,\r
                 mQ35SmramAtDefaultSmbase);\r
   ASSERT_RETURN_ERROR (PcdStatus);\r