OvmfPkg: PlatformPei: allow caching in AddReservedMemoryBaseSizeHob()

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 1ad5bfc26a09a1d6fb09784609d7dc005bacaaa4..0b112751571778b34d0ddf4b03e552fcf77b1182 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -88,7 +88,8 @@ AddIoMemoryBaseSizeHob (
 VOID\r
 AddReservedMemoryBaseSizeHob (\r
   EFI_PHYSICAL_ADDRESS        MemoryBase,\r
-  UINT64                      MemorySize\r
+  UINT64                      MemorySize,\r
+  BOOLEAN                     Cacheable\r
   )\r
 {\r
   BuildResourceDescriptorHob (\r
@@ -96,6 +97,12 @@ AddReservedMemoryBaseSizeHob (
       EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+      (Cacheable ?\r
+       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
+       0\r
+       ) |\r
       EFI_RESOURCE_ATTRIBUTE_TESTED,\r
     MemoryBase,\r
     MemorySize\r
@@ -204,7 +211,20 @@ MemMapInitialization (
 \r
   if (!mXen) {\r
     UINT32  TopOfLowRam;\r
+    UINT32  PciBase;\r
+\r
     TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+      //\r
+      // A 3GB base will always fall into Q35's 32-bit PCI host aperture,\r
+      // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets\r
+      // the RAM below 4 GB exceed it.\r
+      //\r
+      PciBase = BASE_2GB + BASE_1GB;\r
+      ASSERT (TopOfLowRam <= PciBase);\r
+    } else {\r
+      PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
+    }\r
 \r
     //\r
     // address       purpose   size\r
@@ -219,8 +239,7 @@ MemMapInitialization (
     // 0xFED20000    gap                          896 KB\r
     // 0xFEE00000    LAPIC                          1 MB\r
     //\r
-    AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
-                         BASE_2GB : TopOfLowRam, 0xFC000000);\r
+    AddIoMemoryRangeHob (PciBase, 0xFC000000);\r
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
@@ -230,6 +249,68 @@ MemMapInitialization (
   }\r
 }\r
 \r
+EFI_STATUS\r
+GetNamedFwCfgBoolean (\r
+  IN  CHAR8   *FwCfgFileName,\r
+  OUT BOOLEAN *Setting\r
+  )\r
+{\r
+  EFI_STATUS           Status;\r
+  FIRMWARE_CONFIG_ITEM FwCfgItem;\r
+  UINTN                FwCfgSize;\r
+  UINT8                Value[3];\r
+\r
+  Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+  if (FwCfgSize > sizeof Value) {\r
+    return EFI_BAD_BUFFER_SIZE;\r
+  }\r
+  QemuFwCfgSelectItem (FwCfgItem);\r
+  QemuFwCfgReadBytes (FwCfgSize, Value);\r
+\r
+  if ((FwCfgSize == 1) ||\r
+      (FwCfgSize == 2 && Value[1] == '\n') ||\r
+      (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
+    switch (Value[0]) {\r
+      case '0':\r
+      case 'n':\r
+      case 'N':\r
+        *Setting = FALSE;\r
+        return EFI_SUCCESS;\r
+\r
+      case '1':\r
+      case 'y':\r
+      case 'Y':\r
+        *Setting = TRUE;\r
+        return EFI_SUCCESS;\r
+\r
+      default:\r
+        break;\r
+    }\r
+  }\r
+  return EFI_PROTOCOL_ERROR;\r
+}\r
+\r
+#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \\r
+          do {                                                      \\r
+            BOOLEAN Setting;                                        \\r
+                                                                    \\r
+            if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \\r
+                              "opt/ovmf/" #TokenName, &Setting))) { \\r
+              PcdSetBool (TokenName, Setting);                      \\r
+            }                                                       \\r
+          } while (0)\r
+\r
+VOID\r
+NoexecDxeInitialization (\r
+  VOID\r
+  )\r
+{\r
+  UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
+  UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
+}\r
 \r
 VOID\r
 MiscInitialization (\r
@@ -247,9 +328,11 @@ MiscInitialization (
   IoOr8 (0x92, BIT1);\r
 \r
   //\r
-  // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
+  // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
+  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
+  // S3 resume as well, so we build it unconditionally.)\r
   //\r
-  BuildCpuHob (36, 16);\r
+  BuildCpuHob (mPhysMemAddressWidth, 16);\r
 \r
   //\r
   // Determine platform type and save Host Bridge DID to PCD\r
@@ -320,6 +403,7 @@ BootModeInitialization (
   if (CmosRead8 (0xF) == 0xFE) {\r
     mBootMode = BOOT_ON_S3_RESUME;\r
   }\r
+  CmosWrite8 (0xF, 0x00);\r
 \r
   Status = PeiServicesSetBootMode (mBootMode);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -361,7 +445,7 @@ DebugDumpCmos (
   VOID\r
   )\r
 {\r
-  UINTN  Loop;\r
+  UINT32 Loop;\r
 \r
   DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
 \r
@@ -405,6 +489,7 @@ InitializePlatform (
   }\r
 \r
   BootModeInitialization ();\r
+  AddressWidthInitialization ();\r
 \r
   PublishPeiMemory ();\r
 \r
@@ -422,10 +507,9 @@ InitializePlatform (
 \r
   if (mBootMode != BOOT_ON_S3_RESUME) {\r
     ReserveEmuVariableNvStore ();\r
-\r
     PeiFvInitialization ();\r
-\r
     MemMapInitialization ();\r
+    NoexecDxeInitialization ();\r
   }\r
 \r
   MiscInitialization ();\r