#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/Pci22.h>\r
+#include <Guid/XenInfo.h>\r
+#include <IndustryStandard/E820.h>\r
+#include <Library/ResourcePublicationLib.h>\r
+#include <Library/MtrrLib.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
-\r
VOID\r
-MemMapInitialization (\r
- EFI_PHYSICAL_ADDRESS TopOfMemory\r
+XenMemMapInitialization (\r
+ VOID\r
)\r
{\r
+ EFI_E820_ENTRY64 *E820Map;\r
+ UINT32 E820EntriesCount;\r
+ EFI_STATUS Status;\r
+\r
+ DEBUG ((EFI_D_INFO, "Using memory map provided by Xen\n"));\r
+\r
//\r
// Create Memory Type Information HOB\r
//\r
);\r
\r
//\r
- // Add PCI MMIO space available to PCI resource allocations\r
+ // Video memory + Legacy BIOS region\r
//\r
- if (TopOfMemory < BASE_2GB) {\r
- AddIoMemoryBaseSizeHob (BASE_2GB, 0xFC000000 - BASE_2GB);\r
- } else {\r
- AddIoMemoryBaseSizeHob (TopOfMemory, 0xFC000000 - TopOfMemory);\r
+ AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+\r
+ //\r
+ // Parse RAM in E820 map\r
+ //\r
+ Status = XenGetE820Map(&E820Map, &E820EntriesCount);\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (E820EntriesCount > 0) {\r
+ EFI_E820_ENTRY64 *Entry;\r
+ UINT32 Loop;\r
+\r
+ for (Loop = 0; Loop < E820EntriesCount; Loop++) {\r
+ Entry = E820Map + Loop;\r
+\r
+ //\r
+ // Only care about RAM\r
+ //\r
+ if (Entry->Type != EfiAcpiAddressRangeMemory) {\r
+ continue;\r
+ }\r
+\r
+ if (Entry->BaseAddr >= BASE_4GB) {\r
+ AddUntestedMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);\r
+ } else {\r
+ AddMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);\r
+ }\r
+\r
+ MtrrSetMemoryAttribute (Entry->BaseAddr, Entry->Length, CacheWriteBack);\r
+ }\r
}\r
+}\r
+\r
\r
+VOID\r
+MemMapInitialization (\r
+ EFI_PHYSICAL_ADDRESS TopOfMemory\r
+ )\r
+{\r
//\r
- // Local APIC range\r
+ // Create Memory Type Information HOB\r
//\r
- AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB);\r
+ BuildGuidDataHob (\r
+ &gEfiMemoryTypeInformationGuid,\r
+ mDefaultMemoryTypeInformation,\r
+ sizeof(mDefaultMemoryTypeInformation)\r
+ );\r
\r
//\r
- // I/O APIC range\r
+ // Add PCI IO Port space available for PCI resource allocations.\r
//\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB);\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_IO,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
+ 0xC000,\r
+ 0x4000\r
+ );\r
\r
//\r
// Video memory + Legacy BIOS region\r
//\r
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+\r
+ //\r
+ // address purpose size\r
+ // ------------ -------- -------------------------\r
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
+ // 0xFC000000 gap 44 MB\r
+ // 0xFEC00000 IO-APIC 4 KB\r
+ // 0xFEC01000 gap 1020 KB\r
+ // 0xFED00000 HPET 1 KB\r
+ // 0xFED00400 gap 1023 KB\r
+ // 0xFEE00000 LAPIC 1 MB\r
+ //\r
+ AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
}\r
\r
\r
VOID\r
MiscInitialization (\r
- BOOLEAN Xen\r
+ VOID\r
)\r
{\r
//\r
//\r
BuildCpuHob (36, 16);\r
\r
- if (!Xen) {\r
+ //\r
+ // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
+ // example by Xen) and skip the setup here. This matches the logic in\r
+ // AcpiTimerLibConstructor ().\r
+ //\r
+ if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
+ //\r
+ // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+ // 1. set PMBA\r
+ //\r
+ PciAndThenOr32 (\r
+ PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
+ (UINT32) ~0xFFC0,\r
+ PcdGet16 (PcdAcpiPmBaseAddress)\r
+ );\r
+\r
//\r
- // Set the PM I/O base address to 0x400\r
+ // 2. set PCICMD/IOSE\r
//\r
- PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);\r
+ PciOr8 (\r
+ PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
+ EFI_PCI_COMMAND_IO_SPACE\r
+ );\r
+\r
+ //\r
+ // 3. set PMREGMISC/PMIOSE\r
+ //\r
+ PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
}\r
}\r
\r
//\r
VariableStore =\r
(EFI_PHYSICAL_ADDRESS)(UINTN)\r
- AllocateRuntimePool (\r
- 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
+ AllocateAlignedRuntimePages (\r
+ EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
);\r
DEBUG ((EFI_D_INFO,\r
"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- EFI_STATUS Status;\r
EFI_PHYSICAL_ADDRESS TopOfMemory;\r
- BOOLEAN Xen;\r
+ UINT32 XenLeaf;\r
+\r
+ TopOfMemory = 0;\r
\r
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
DebugDumpCmos ();\r
\r
- TopOfMemory = MemDetect ();\r
+ XenLeaf = XenDetect ();\r
\r
- Status = InitializeXen ();\r
- Xen = EFI_ERROR (Status) ? FALSE : TRUE;\r
+ PublishPeiMemory ();\r
+\r
+ if (XenLeaf != 0) {\r
+ PcdSetBool (PcdPciDisableBusEnumeration, TRUE);\r
+ } else {\r
+ TopOfMemory = MemDetect ();\r
+ }\r
+\r
+ if (XenLeaf != 0) {\r
+ DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
+ InitializeXen (XenLeaf);\r
+ }\r
\r
ReserveEmuVariableNvStore ();\r
\r
PeiFvInitialization ();\r
\r
- MemMapInitialization (TopOfMemory);\r
+ if (XenLeaf != 0) {\r
+ XenMemMapInitialization ();\r
+ } else {\r
+ MemMapInitialization (TopOfMemory);\r
+ }\r
\r
- MiscInitialization (Xen);\r
+ MiscInitialization ();\r
\r
BootModeInitialization ();\r
\r
projects / mirror_edk2.git / blobdiff