OvmfPkg/AcpiPlatformDxe: Assert if AcpiTable protocol is not found

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 00c688d68a9142284b422b80d062f7c7abc0e657..1940e01640fd177aa5646ed7b7ed07e96fd11c73 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -35,6 +35,7 @@
 #include <Guid/MemoryTypeInformation.h>\r
 #include <Ppi/MasterBootMode.h>\r
 #include <IndustryStandard/Pci22.h>\r
+#include <OvmfPlatforms.h>\r
 \r
 #include "Platform.h"\r
 #include "Cmos.h"\r
@@ -228,6 +229,11 @@ MiscInitialization (
   VOID\r
   )\r
 {\r
+  UINT16 HostBridgeDevId;\r
+  UINTN  PmCmd;\r
+  UINTN  Pmba;\r
+  UINTN  PmRegMisc;\r
+\r
   //\r
   // Disable A20 Mask\r
   //\r
@@ -238,34 +244,50 @@ MiscInitialization (
   //\r
   BuildCpuHob (36, 16);\r
 \r
+  //\r
+  // Query Host Bridge DID to determine platform type and save to PCD\r
+  //\r
+  HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+  switch (HostBridgeDevId) {\r
+    case INTEL_82441_DEVICE_ID:\r
+      PmCmd     = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
+      Pmba      = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r
+      break;\r
+    case INTEL_Q35_MCH_DEVICE_ID:\r
+      PmCmd     = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
+      Pmba      = POWER_MGMT_REGISTER_Q35 (0x40);\r
+      PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r
+      break;\r
+    default:\r
+      DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+        __FUNCTION__, HostBridgeDevId));\r
+      ASSERT (FALSE);\r
+      return;\r
+  }\r
+  PcdSet16 (PcdOvmfHostBridgePciDevId, HostBridgeDevId);\r
+\r
   //\r
   // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
   // example by Xen) and skip the setup here. This matches the logic in\r
   // AcpiTimerLibConstructor ().\r
   //\r
-  if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
+  if ((PciRead8 (PmRegMisc) & 0x01) == 0) {\r
     //\r
     // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
     // 1. set PMBA\r
     //\r
-    PciAndThenOr32 (\r
-      PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
-      (UINT32) ~0xFFC0,\r
-      PcdGet16 (PcdAcpiPmBaseAddress)\r
-      );\r
+    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
 \r
     //\r
     // 2. set PCICMD/IOSE\r
     //\r
-    PciOr8 (\r
-      PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
-      EFI_PCI_COMMAND_IO_SPACE\r
-      );\r
+    PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
 \r
     //\r
     // 3. set PMREGMISC/PMIOSE\r
     //\r
-    PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
+    PciOr8 (PmRegMisc, 0x01);\r
   }\r
 }\r
 \r
@@ -375,11 +397,13 @@ InitializePlatform (
     InitializeXen ();\r
   }\r
 \r
-  ReserveEmuVariableNvStore ();\r
+  if (mBootMode != BOOT_ON_S3_RESUME) {\r
+    ReserveEmuVariableNvStore ();\r
 \r
-  PeiFvInitialization ();\r
+    PeiFvInitialization ();\r
 \r
-  MemMapInitialization ();\r
+    MemMapInitialization ();\r
+  }\r
 \r
   MiscInitialization ();\r
 \r