/**@file\r
Platform PEI driver\r
\r
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/QemuFwCfgLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
+#include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/Pci22.h>\r
+#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
};\r
\r
\r
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+ &gEfiPeiMasterBootModePpiGuid,\r
+ NULL\r
+ }\r
+};\r
+\r
+\r
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+\r
+BOOLEAN mS3Supported = FALSE;\r
+\r
+\r
VOID\r
AddIoMemoryBaseSizeHob (\r
EFI_PHYSICAL_ADDRESS MemoryBase,\r
);\r
}\r
\r
+VOID\r
+AddReservedMemoryBaseSizeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
+ )\r
+{\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_MEMORY_RESERVED,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+ MemoryBase,\r
+ MemorySize\r
+ );\r
+}\r
\r
VOID\r
AddIoMemoryRangeHob (\r
AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
-\r
VOID\r
MemMapInitialization (\r
- EFI_PHYSICAL_ADDRESS TopOfMemory\r
+ VOID\r
)\r
{\r
//\r
//\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- 0x1000,\r
- 0xF000\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
+ 0xC000,\r
+ 0x4000\r
);\r
\r
- //\r
- // Add PCI MMIO space available to PCI resource allocations\r
- //\r
- if (TopOfMemory < BASE_2GB) {\r
- AddIoMemoryBaseSizeHob (BASE_2GB, 0xFEC00000 - BASE_2GB);\r
- } else {\r
- AddIoMemoryBaseSizeHob (TopOfMemory, 0xFEC00000 - TopOfMemory);\r
- }\r
-\r
- //\r
- // Local APIC range\r
- //\r
- AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB);\r
-\r
- //\r
- // I/O APIC range\r
- //\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB);\r
-\r
//\r
// Video memory + Legacy BIOS region\r
//\r
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+\r
+ if (!mXen) {\r
+ UINT32 TopOfLowRam;\r
+ TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+\r
+ //\r
+ // address purpose size\r
+ // ------------ -------- -------------------------\r
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
+ // 0xFC000000 gap 44 MB\r
+ // 0xFEC00000 IO-APIC 4 KB\r
+ // 0xFEC01000 gap 1020 KB\r
+ // 0xFED00000 HPET 1 KB\r
+ // 0xFED00400 gap 1023 KB\r
+ // 0xFEE00000 LAPIC 1 MB\r
+ //\r
+ AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
+ BASE_2GB : TopOfLowRam, 0xFC000000);\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+ }\r
}\r
\r
\r
VOID\r
MiscInitialization (\r
+ VOID\r
)\r
{\r
+ UINT16 HostBridgeDevId;\r
+ UINTN PmCmd;\r
+ UINTN Pmba;\r
+ UINTN PmRegMisc;\r
+\r
//\r
// Disable A20 Mask\r
//\r
BuildCpuHob (36, 16);\r
\r
//\r
- // Set the PM I/O base address to 0x400\r
+ // Query Host Bridge DID to determine platform type and save to PCD\r
+ //\r
+ HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+ switch (HostBridgeDevId) {\r
+ case INTEL_82441_DEVICE_ID:\r
+ PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+ PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r
+ break;\r
+ case INTEL_Q35_MCH_DEVICE_ID:\r
+ PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
+ PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r
+ break;\r
+ default:\r
+ DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+ __FUNCTION__, HostBridgeDevId));\r
+ ASSERT (FALSE);\r
+ return;\r
+ }\r
+ PcdSet16 (PcdOvmfHostBridgePciDevId, HostBridgeDevId);\r
+\r
+ //\r
+ // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
+ // example by Xen) and skip the setup here. This matches the logic in\r
+ // AcpiTimerLibConstructor ().\r
//\r
- PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);\r
+ if ((PciRead8 (PmRegMisc) & 0x01) == 0) {\r
+ //\r
+ // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+ // 1. set PMBA\r
+ //\r
+ PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
+\r
+ //\r
+ // 2. set PCICMD/IOSE\r
+ //\r
+ PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
+\r
+ //\r
+ // 3. set PMREGMISC/PMIOSE\r
+ //\r
+ PciOr8 (PmRegMisc, 0x01);\r
+ }\r
+}\r
+\r
+\r
+VOID\r
+BootModeInitialization (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ if (CmosRead8 (0xF) == 0xFE) {\r
+ mBootMode = BOOT_ON_S3_RESUME;\r
+ }\r
+\r
+ Status = PeiServicesSetBootMode (mBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = PeiServicesInstallPpi (mPpiBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
//\r
VariableStore =\r
(EFI_PHYSICAL_ADDRESS)(UINTN)\r
- AllocateRuntimePool (\r
- 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
+ AllocateAlignedRuntimePages (\r
+ EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
);\r
DEBUG ((EFI_D_INFO,\r
"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- EFI_PHYSICAL_ADDRESS TopOfMemory;\r
-\r
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
DebugDumpCmos ();\r
\r
- TopOfMemory = MemDetect ();\r
+ XenDetect ();\r
\r
- ReserveEmuVariableNvStore ();\r
+ if (QemuFwCfgS3Enabled ()) {\r
+ DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
+ mS3Supported = TRUE;\r
+ }\r
+\r
+ BootModeInitialization ();\r
+\r
+ PublishPeiMemory ();\r
+\r
+ InitializeRamRegions ();\r
\r
- PeiFvInitialization ();\r
+ if (mXen) {\r
+ DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
+ InitializeXen ();\r
+ }\r
+\r
+ if (mBootMode != BOOT_ON_S3_RESUME) {\r
+ ReserveEmuVariableNvStore ();\r
\r
- MemMapInitialization (TopOfMemory);\r
+ PeiFvInitialization ();\r
+\r
+ MemMapInitialization ();\r
+ }\r
\r
MiscInitialization ();\r
\r
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