OvmfPkg: PlatformPei: set SMBIOS entry point version dynamically

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 5ce0a9099a4a0cf7c79a651f202268e0c99f1adb..210578796129925f54a8dccd27dafd56ebdbef1a 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -32,9 +32,11 @@
 #include <Library/PeiServicesLib.h>\r
 #include <Library/QemuFwCfgLib.h>\r
 #include <Library/ResourcePublicationLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
 #include <Guid/MemoryTypeInformation.h>\r
 #include <Ppi/MasterBootMode.h>\r
 #include <IndustryStandard/Pci22.h>\r
+#include <IndustryStandard/SmBios.h>\r
 #include <OvmfPlatforms.h>\r
 \r
 #include "Platform.h"\r
@@ -61,6 +63,8 @@ EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
 };\r
 \r
 \r
+UINT16 mHostBridgeDevId;\r
+\r
 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
 \r
 BOOLEAN mS3Supported = FALSE;\r
@@ -212,13 +216,18 @@ MemMapInitialization (
     // 0xFEC00000    IO-APIC                        4 KB\r
     // 0xFEC01000    gap                         1020 KB\r
     // 0xFED00000    HPET                           1 KB\r
-    // 0xFED00400    gap                         1023 KB\r
+    // 0xFED00400    gap                          111 KB\r
+    // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
+    // 0xFED20000    gap                          896 KB\r
     // 0xFEE00000    LAPIC                          1 MB\r
     //\r
     AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
                          BASE_2GB : TopOfLowRam, 0xFC000000);\r
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+      AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+    }\r
     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
   }\r
 }\r
@@ -229,7 +238,6 @@ MiscInitialization (
   VOID\r
   )\r
 {\r
-  UINT16 HostBridgeDevId;\r
   UINTN  PmCmd;\r
   UINTN  Pmba;\r
   UINTN  AcpiCtlReg;\r
@@ -246,29 +254,28 @@ MiscInitialization (
   BuildCpuHob (36, 16);\r
 \r
   //\r
-  // Query Host Bridge DID to determine platform type and save to PCD\r
+  // Determine platform type and save Host Bridge DID to PCD\r
   //\r
-  HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
-  switch (HostBridgeDevId) {\r
+  switch (mHostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
-      Pmba       = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
-      AcpiEnBit  = BIT0; // PIIX4_PMIOSE\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
-      Pmba       = POWER_MGMT_REGISTER_Q35 (0x40);\r
-      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
-      AcpiEnBit  = BIT7; // Q35_ACPI_EN\r
+      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
       break;\r
     default:\r
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
-        __FUNCTION__, HostBridgeDevId));\r
+        __FUNCTION__, mHostBridgeDevId));\r
       ASSERT (FALSE);\r
       return;\r
   }\r
-  PcdSet16 (PcdOvmfHostBridgePciDevId, HostBridgeDevId);\r
+  PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
 \r
   //\r
   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
@@ -292,6 +299,16 @@ MiscInitialization (
     //\r
     PciOr8 (AcpiCtlReg, AcpiEnBit);\r
   }\r
+\r
+  if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+    //\r
+    // Set Root Complex Register Block BAR\r
+    //\r
+    PciWrite32 (\r
+      POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
+      ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
+      );\r
+  }\r
 }\r
 \r
 \r
@@ -362,6 +379,41 @@ DebugDumpCmos (
 }\r
 \r
 \r
+/**\r
+  Set the SMBIOS entry point version for the generic SmbiosDxe driver.\r
+**/\r
+STATIC\r
+VOID\r
+SmbiosVersionInitialization (\r
+  VOID\r
+  )\r
+{\r
+  FIRMWARE_CONFIG_ITEM     Anchor;\r
+  UINTN                    AnchorSize;\r
+  SMBIOS_TABLE_ENTRY_POINT QemuAnchor;\r
+  UINT16                   SmbiosVersion;\r
+\r
+  if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,\r
+                      &AnchorSize)) ||\r
+      AnchorSize != sizeof QemuAnchor) {\r
+    return;\r
+  }\r
+\r
+  QemuFwCfgSelectItem (Anchor);\r
+  QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);\r
+  if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 ||\r
+      CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {\r
+    return;\r
+  }\r
+\r
+  SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 |\r
+                           QemuAnchor.MinorVersion);\r
+  DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,\r
+    SmbiosVersion));\r
+  PcdSet16 (PcdSmbiosVersion, SmbiosVersion);\r
+}\r
+\r
+\r
 /**\r
   Perform Platform PEI initialization.\r
 \r
@@ -400,12 +452,19 @@ InitializePlatform (
     InitializeXen ();\r
   }\r
 \r
+  //\r
+  // Query Host Bridge DID\r
+  //\r
+  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+\r
   if (mBootMode != BOOT_ON_S3_RESUME) {\r
     ReserveEmuVariableNvStore ();\r
 \r
     PeiFvInitialization ();\r
 \r
     MemMapInitialization ();\r
+\r
+    SmbiosVersionInitialization ();\r
   }\r
 \r
   MiscInitialization ();\r