OvmfPkg/Csm/LegacyBiosDxe: Fix Legacy16GetTableAddress call for E820 data

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index fd8eccaf3e50cc133cfc1acb3adb949afc324fa1..3ba2459872d93d48ca9258fb12c1587ad0751d20 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -181,18 +181,18 @@ MemMapInitialization (
 \r
     TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
     PciExBarBase = 0;\r
-    PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
       //\r
-      // The 32-bit PCI host aperture is expected to fall between the top of\r
-      // low RAM and the base of the MMCONFIG area.\r
+      // The MMCONFIG area is expected to fall between the top of low RAM and\r
+      // the base of the 32-bit PCI host aperture.\r
       //\r
       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
-      ASSERT (PciBase < PciExBarBase);\r
+      ASSERT (TopOfLowRam <= PciExBarBase);\r
       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
-      PciSize = (UINT32)(PciExBarBase - PciBase);\r
+      PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
     } else {\r
-      PciSize = 0xFC000000 - PciBase;\r
+      ASSERT (TopOfLowRam <= mQemuUc32Base);\r
+      PciBase = mQemuUc32Base;\r
     }\r
 \r
     //\r
@@ -208,6 +208,7 @@ MemMapInitialization (
     // 0xFED20000    gap                          896 KB\r
     // 0xFEE00000    LAPIC                          1 MB\r
     //\r
+    PciSize = 0xFC000000 - PciBase;\r
     AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
     ASSERT_RETURN_ERROR (PcdStatus);\r
@@ -650,6 +651,8 @@ InitializePlatform (
 \r
   PublishPeiMemory ();\r
 \r
+  QemuUc32BaseInitialization ();\r
+\r
   InitializeRamRegions ();\r
 \r
   if (mXen) {\r