#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
+#include <Library/QemuFwCfgS3Lib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
\r
BOOLEAN mS3Supported = FALSE;\r
\r
+UINT32 mMaxCpuCount;\r
\r
VOID\r
AddIoMemoryBaseSizeHob (\r
//\r
VariableStore =\r
(EFI_PHYSICAL_ADDRESS)(UINTN)\r
- AllocateAlignedRuntimePages (\r
- EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
- PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
+ AllocateRuntimePages (\r
+ EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
);\r
DEBUG ((EFI_D_INFO,\r
"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
}\r
\r
\r
+/**\r
+ Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r
+ Set the mMaxCpuCount variable.\r
+**/\r
+VOID\r
+MaxCpuCountInitialization (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 ProcessorCount;\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
+ ProcessorCount = QemuFwCfgRead16 ();\r
+ //\r
+ // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r
+ // from the PCD default. No change to PCDs.\r
+ //\r
+ if (ProcessorCount == 0) {\r
+ mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
+ return;\r
+ }\r
+ //\r
+ // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r
+ //\r
+ mMaxCpuCount = ProcessorCount;\r
+ //\r
+ // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r
+ // to wait, in the initial AP bringup, exactly as long as it takes for all of\r
+ // the APs to report in. For this, we set the longest representable timeout\r
+ // (approx. 71 minutes).\r
+ //\r
+ PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r
+ ProcessorCount));\r
+}\r
+\r
+\r
/**\r
Perform Platform PEI initialization.\r
\r
S3Verification ();\r
BootModeInitialization ();\r
AddressWidthInitialization ();\r
+ MaxCpuCountInitialization ();\r
\r
PublishPeiMemory ();\r
\r
mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
- ReserveEmuVariableNvStore ();\r
+ if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ ReserveEmuVariableNvStore ();\r
+ }\r
PeiFvInitialization ();\r
MemMapInitialization ();\r
NoexecDxeInitialization ();\r