OvmfPkg/PlatformPei: align EmuVariableNvStore at any page boundary

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index ca1e6dc7e320169c1611a9de81c71e85c875fc6b..3e9fda7c7ab019c11fe4b32b5ca75d7a33a88196 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -32,6 +32,7 @@
 #include <Library/PeimEntryPoint.h>\r
 #include <Library/PeiServicesLib.h>\r
 #include <Library/QemuFwCfgLib.h>\r
+#include <Library/QemuFwCfgS3Lib.h>\r
 #include <Library/ResourcePublicationLib.h>\r
 #include <Guid/MemoryTypeInformation.h>\r
 #include <Ppi/MasterBootMode.h>\r
@@ -68,6 +69,7 @@ EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
 \r
 BOOLEAN mS3Supported = FALSE;\r
 \r
+UINT32 mMaxCpuCount;\r
 \r
 VOID\r
 AddIoMemoryBaseSizeHob (\r
@@ -156,8 +158,9 @@ MemMapInitialization (
   VOID\r
   )\r
 {\r
-  UINT64 PciIoBase;\r
-  UINT64 PciIoSize;\r
+  UINT64        PciIoBase;\r
+  UINT64        PciIoSize;\r
+  RETURN_STATUS PcdStatus;\r
 \r
   PciIoBase = 0xC000;\r
   PciIoSize = 0x4000;\r
@@ -212,8 +215,11 @@ MemMapInitialization (
     //\r
     PciSize = 0xFC000000 - PciBase;\r
     AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
-    PcdSet64 (PcdPciMmio32Base, PciBase);\r
-    PcdSet64 (PcdPciMmio32Size, PciSize);\r
+    PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
+    ASSERT_RETURN_ERROR (PcdStatus);\r
+    PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
+    ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
@@ -266,8 +272,10 @@ MemMapInitialization (
     PciIoBase,\r
     PciIoSize\r
     );\r
-  PcdSet64 (PcdPciIoBase, PciIoBase);\r
-  PcdSet64 (PcdPciIoSize, PciIoSize);\r
+  PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
+  PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
 }\r
 \r
 EFI_STATUS\r
@@ -316,11 +324,13 @@ GetNamedFwCfgBoolean (
 \r
 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \\r
           do {                                                      \\r
-            BOOLEAN Setting;                                        \\r
+            BOOLEAN       Setting;                                  \\r
+            RETURN_STATUS PcdStatus;                                \\r
                                                                     \\r
             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \\r
                               "opt/ovmf/" #TokenName, &Setting))) { \\r
-              PcdSetBool (TokenName, Setting);                      \\r
+              PcdStatus = PcdSetBoolS (TokenName, Setting);         \\r
+              ASSERT_RETURN_ERROR (PcdStatus);                      \\r
             }                                                       \\r
           } while (0)\r
 \r
@@ -379,12 +389,13 @@ MiscInitialization (
   VOID\r
   )\r
 {\r
-  UINTN  PmCmd;\r
-  UINTN  Pmba;\r
-  UINT32 PmbaAndVal;\r
-  UINT32 PmbaOrVal;\r
-  UINTN  AcpiCtlReg;\r
-  UINT8  AcpiEnBit;\r
+  UINTN         PmCmd;\r
+  UINTN         Pmba;\r
+  UINT32        PmbaAndVal;\r
+  UINT32        PmbaOrVal;\r
+  UINTN         AcpiCtlReg;\r
+  UINT8         AcpiEnBit;\r
+  RETURN_STATUS PcdStatus;\r
 \r
   //\r
   // Disable A20 Mask\r
@@ -424,7 +435,8 @@ MiscInitialization (
       ASSERT (FALSE);\r
       return;\r
   }\r
-  PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+  PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
 \r
   //\r
   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
@@ -491,6 +503,7 @@ ReserveEmuVariableNvStore (
   )\r
 {\r
   EFI_PHYSICAL_ADDRESS VariableStore;\r
+  RETURN_STATUS        PcdStatus;\r
 \r
   //\r
   // Allocate storage for NV variables early on so it will be\r
@@ -500,16 +513,16 @@ ReserveEmuVariableNvStore (
   //\r
   VariableStore =\r
     (EFI_PHYSICAL_ADDRESS)(UINTN)\r
-      AllocateAlignedRuntimePages (\r
-        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
-        PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
+      AllocateRuntimePages (\r
+        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
         );\r
   DEBUG ((EFI_D_INFO,\r
           "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
           VariableStore,\r
           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
         ));\r
-  PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
+  PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
 }\r
 \r
 \r
@@ -555,6 +568,47 @@ S3Verification (
 }\r
 \r
 \r
+/**\r
+  Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r
+  Set the mMaxCpuCount variable.\r
+**/\r
+VOID\r
+MaxCpuCountInitialization (\r
+  VOID\r
+  )\r
+{\r
+  UINT16        ProcessorCount;\r
+  RETURN_STATUS PcdStatus;\r
+\r
+  QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
+  ProcessorCount = QemuFwCfgRead16 ();\r
+  //\r
+  // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r
+  // from the PCD default. No change to PCDs.\r
+  //\r
+  if (ProcessorCount == 0) {\r
+    mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
+    return;\r
+  }\r
+  //\r
+  // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r
+  //\r
+  mMaxCpuCount = ProcessorCount;\r
+  //\r
+  // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r
+  // to wait, in the initial AP bringup, exactly as long as it takes for all of\r
+  // the APs to report in. For this, we set the longest representable timeout\r
+  // (approx. 71 minutes).\r
+  //\r
+  PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
+  PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
+  DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r
+    ProcessorCount));\r
+}\r
+\r
+\r
 /**\r
   Perform Platform PEI initialization.\r
 \r
@@ -589,6 +643,7 @@ InitializePlatform (
   S3Verification ();\r
   BootModeInitialization ();\r
   AddressWidthInitialization ();\r
+  MaxCpuCountInitialization ();\r
 \r
   PublishPeiMemory ();\r
 \r
@@ -605,7 +660,9 @@ InitializePlatform (
   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
 \r
   if (mBootMode != BOOT_ON_S3_RESUME) {\r
-    ReserveEmuVariableNvStore ();\r
+    if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
+      ReserveEmuVariableNvStore ();\r
+    }\r
     PeiFvInitialization ();\r
     MemMapInitialization ();\r
     NoexecDxeInitialization ();\r