#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
+#include <Library/QemuFwCfgLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/Pci22.h>\r
-#include <Guid/XenInfo.h>\r
-#include <IndustryStandard/E820.h>\r
-#include <Library/ResourcePublicationLib.h>\r
-#include <Library/MtrrLib.h>\r
+#include <IndustryStandard/SmBios.h>\r
+#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
};\r
\r
\r
+UINT16 mHostBridgeDevId;\r
+\r
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+\r
+BOOLEAN mS3Supported = FALSE;\r
+\r
+\r
VOID\r
AddIoMemoryBaseSizeHob (\r
EFI_PHYSICAL_ADDRESS MemoryBase,\r
}\r
\r
VOID\r
-XenMemMapInitialization (\r
+MemMapInitialization (\r
VOID\r
)\r
{\r
- EFI_E820_ENTRY64 *E820Map;\r
- UINT32 E820EntriesCount;\r
- EFI_STATUS Status;\r
-\r
- DEBUG ((EFI_D_INFO, "Using memory map provided by Xen\n"));\r
-\r
//\r
// Create Memory Type Information HOB\r
//\r
//\r
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
- //\r
- // Parse RAM in E820 map\r
- //\r
- Status = XenGetE820Map(&E820Map, &E820EntriesCount);\r
-\r
- ASSERT_EFI_ERROR (Status);\r
+ if (!mXen) {\r
+ UINT32 TopOfLowRam;\r
+ TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
\r
- if (E820EntriesCount > 0) {\r
- EFI_E820_ENTRY64 *Entry;\r
- UINT32 Loop;\r
-\r
- for (Loop = 0; Loop < E820EntriesCount; Loop++) {\r
- Entry = E820Map + Loop;\r
-\r
- //\r
- // Only care about RAM\r
- //\r
- if (Entry->Type != EfiAcpiAddressRangeMemory) {\r
- continue;\r
- }\r
-\r
- if (Entry->BaseAddr >= BASE_4GB) {\r
- AddUntestedMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);\r
- } else {\r
- AddMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);\r
- }\r
-\r
- MtrrSetMemoryAttribute (Entry->BaseAddr, Entry->Length, CacheWriteBack);\r
+ //\r
+ // address purpose size\r
+ // ------------ -------- -------------------------\r
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
+ // 0xFC000000 gap 44 MB\r
+ // 0xFEC00000 IO-APIC 4 KB\r
+ // 0xFEC01000 gap 1020 KB\r
+ // 0xFED00000 HPET 1 KB\r
+ // 0xFED00400 gap 111 KB\r
+ // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
+ // 0xFED20000 gap 896 KB\r
+ // 0xFEE00000 LAPIC 1 MB\r
+ //\r
+ AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
+ BASE_2GB : TopOfLowRam, 0xFC000000);\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
}\r
+ AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
}\r
}\r
\r
\r
-VOID\r
-MemMapInitialization (\r
- EFI_PHYSICAL_ADDRESS TopOfMemory\r
- )\r
-{\r
- //\r
- // Create Memory Type Information HOB\r
- //\r
- BuildGuidDataHob (\r
- &gEfiMemoryTypeInformationGuid,\r
- mDefaultMemoryTypeInformation,\r
- sizeof(mDefaultMemoryTypeInformation)\r
- );\r
-\r
- //\r
- // Add PCI IO Port space available for PCI resource allocations.\r
- //\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- 0xC000,\r
- 0x4000\r
- );\r
-\r
- //\r
- // Video memory + Legacy BIOS region\r
- //\r
- AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
-\r
- //\r
- // address purpose size\r
- // ------------ -------- -------------------------\r
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
- // 0xFC000000 gap 44 MB\r
- // 0xFEC00000 IO-APIC 4 KB\r
- // 0xFEC01000 gap 1020 KB\r
- // 0xFED00000 HPET 1 KB\r
- // 0xFED00400 gap 1023 KB\r
- // 0xFEE00000 LAPIC 1 MB\r
- //\r
- AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
- AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
- AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
-}\r
-\r
-\r
VOID\r
MiscInitialization (\r
VOID\r
)\r
{\r
+ UINTN PmCmd;\r
+ UINTN Pmba;\r
+ UINTN AcpiCtlReg;\r
+ UINT8 AcpiEnBit;\r
+\r
//\r
// Disable A20 Mask\r
//\r
IoOr8 (0x92, BIT1);\r
\r
//\r
- // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
+ // S3 resume as well, so we build it unconditionally.)\r
+ //\r
+ BuildCpuHob (mPhysMemAddressWidth, 16);\r
+\r
+ //\r
+ // Determine platform type and save Host Bridge DID to PCD\r
//\r
- BuildCpuHob (36, 16);\r
+ switch (mHostBridgeDevId) {\r
+ case INTEL_82441_DEVICE_ID:\r
+ PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
+ break;\r
+ case INTEL_Q35_MCH_DEVICE_ID:\r
+ PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
+ break;\r
+ default:\r
+ DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+ __FUNCTION__, mHostBridgeDevId));\r
+ ASSERT (FALSE);\r
+ return;\r
+ }\r
+ PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
\r
//\r
- // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
- // example by Xen) and skip the setup here. This matches the logic in\r
- // AcpiTimerLibConstructor ().\r
+ // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
+ // has been configured (e.g., by Xen) and skip the setup here.\r
+ // This matches the logic in AcpiTimerLibConstructor ().\r
//\r
- if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
+ if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
//\r
- // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+ // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
// 1. set PMBA\r
//\r
- PciAndThenOr32 (\r
- PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
- (UINT32) ~0xFFC0,\r
- PcdGet16 (PcdAcpiPmBaseAddress)\r
- );\r
+ PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
\r
//\r
// 2. set PCICMD/IOSE\r
//\r
- PciOr8 (\r
- PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
- EFI_PCI_COMMAND_IO_SPACE\r
- );\r
+ PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
+\r
+ //\r
+ // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
+ //\r
+ PciOr8 (AcpiCtlReg, AcpiEnBit);\r
+ }\r
\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
- // 3. set PMREGMISC/PMIOSE\r
+ // Set Root Complex Register Block BAR\r
//\r
- PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
+ PciWrite32 (\r
+ POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
+ ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
+ );\r
}\r
}\r
\r
\r
VOID\r
BootModeInitialization (\r
+ VOID\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
+\r
+ if (CmosRead8 (0xF) == 0xFE) {\r
+ mBootMode = BOOT_ON_S3_RESUME;\r
+ }\r
\r
- Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
+ Status = PeiServicesSetBootMode (mBootMode);\r
ASSERT_EFI_ERROR (Status);\r
\r
Status = PeiServicesInstallPpi (mPpiBootMode);\r
VOID\r
)\r
{\r
- UINTN Loop;\r
+ UINT32 Loop;\r
\r
DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
\r
}\r
\r
\r
+/**\r
+ Set the SMBIOS entry point version for the generic SmbiosDxe driver.\r
+**/\r
+STATIC\r
+VOID\r
+SmbiosVersionInitialization (\r
+ VOID\r
+ )\r
+{\r
+ FIRMWARE_CONFIG_ITEM Anchor;\r
+ UINTN AnchorSize;\r
+ SMBIOS_TABLE_ENTRY_POINT QemuAnchor;\r
+ UINT16 SmbiosVersion;\r
+\r
+ if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,\r
+ &AnchorSize)) ||\r
+ AnchorSize != sizeof QemuAnchor) {\r
+ return;\r
+ }\r
+\r
+ QemuFwCfgSelectItem (Anchor);\r
+ QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);\r
+ if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 ||\r
+ CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {\r
+ return;\r
+ }\r
+\r
+ SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 |\r
+ QemuAnchor.MinorVersion);\r
+ DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,\r
+ SmbiosVersion));\r
+ PcdSet16 (PcdSmbiosVersion, SmbiosVersion);\r
+}\r
+\r
+\r
/**\r
Perform Platform PEI initialization.\r
\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- EFI_PHYSICAL_ADDRESS TopOfMemory;\r
-\r
- TopOfMemory = 0;\r
-\r
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
DebugDumpCmos ();\r
\r
XenDetect ();\r
\r
+ if (QemuFwCfgS3Enabled ()) {\r
+ DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
+ mS3Supported = TRUE;\r
+ }\r
+\r
BootModeInitialization ();\r
+ AddressWidthInitialization ();\r
\r
PublishPeiMemory ();\r
\r
- if (mXen) {\r
- PcdSetBool (PcdPciDisableBusEnumeration, TRUE);\r
- } else {\r
- TopOfMemory = MemDetect ();\r
- }\r
+ InitializeRamRegions ();\r
\r
if (mXen) {\r
DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
InitializeXen ();\r
}\r
\r
- ReserveEmuVariableNvStore ();\r
+ //\r
+ // Query Host Bridge DID\r
+ //\r
+ mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
- PeiFvInitialization ();\r
+ if (mBootMode != BOOT_ON_S3_RESUME) {\r
+ ReserveEmuVariableNvStore ();\r
\r
- if (mXen) {\r
- XenMemMapInitialization ();\r
- } else {\r
- MemMapInitialization (TopOfMemory);\r
+ PeiFvInitialization ();\r
+\r
+ MemMapInitialization ();\r
+\r
+ SmbiosVersionInitialization ();\r
}\r
\r
MiscInitialization ();\r
projects / mirror_edk2.git / blobdiff