/**@file\r
Platform PEI driver\r
\r
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/QemuFwCfgLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
+#include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/Pci22.h>\r
+#include <IndustryStandard/SmBios.h>\r
+#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
+#include "Cmos.h"\r
\r
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
{ EfiACPIMemoryNVS, 0x004 },\r
};\r
\r
\r
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+ &gEfiPeiMasterBootModePpiGuid,\r
+ NULL\r
+ }\r
+};\r
+\r
+\r
+UINT16 mHostBridgeDevId;\r
+\r
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+\r
+BOOLEAN mS3Supported = FALSE;\r
+\r
+\r
VOID\r
AddIoMemoryBaseSizeHob (\r
EFI_PHYSICAL_ADDRESS MemoryBase,\r
);\r
}\r
\r
+VOID\r
+AddReservedMemoryBaseSizeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
+ )\r
+{\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_MEMORY_RESERVED,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+ MemoryBase,\r
+ MemorySize\r
+ );\r
+}\r
\r
VOID\r
AddIoMemoryRangeHob (\r
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
+\r
+VOID\r
+AddUntestedMemoryBaseSizeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
+ )\r
+{\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
+ MemoryBase,\r
+ MemorySize\r
+ );\r
+}\r
+\r
+\r
+VOID\r
+AddUntestedMemoryRangeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ EFI_PHYSICAL_ADDRESS MemoryLimit\r
+ )\r
+{\r
+ AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
+}\r
+\r
VOID\r
MemMapInitialization (\r
- EFI_PHYSICAL_ADDRESS TopOfMemory\r
+ VOID\r
)\r
{\r
//\r
//\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- 0x1000,\r
- 0xF000\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
+ 0xC000,\r
+ 0x4000\r
);\r
\r
- //\r
- // Add PCI MMIO space available to PCI resource allocations\r
- //\r
- if (TopOfMemory < BASE_2GB) {\r
- AddIoMemoryBaseSizeHob (BASE_2GB, 0xFEC00000 - BASE_2GB);\r
- } else {\r
- AddIoMemoryBaseSizeHob (TopOfMemory, 0xFEC00000 - TopOfMemory);\r
- }\r
-\r
- //\r
- // Local APIC range\r
- //\r
- AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB);\r
-\r
- //\r
- // I/O APIC range\r
- //\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB);\r
-\r
//\r
// Video memory + Legacy BIOS region\r
//\r
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+\r
+ if (!mXen) {\r
+ UINT32 TopOfLowRam;\r
+ TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+\r
+ //\r
+ // address purpose size\r
+ // ------------ -------- -------------------------\r
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
+ // 0xFC000000 gap 44 MB\r
+ // 0xFEC00000 IO-APIC 4 KB\r
+ // 0xFEC01000 gap 1020 KB\r
+ // 0xFED00000 HPET 1 KB\r
+ // 0xFED00400 gap 111 KB\r
+ // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
+ // 0xFED20000 gap 896 KB\r
+ // 0xFEE00000 LAPIC 1 MB\r
+ //\r
+ AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
+ BASE_2GB : TopOfLowRam, 0xFC000000);\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+ }\r
+ AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+ }\r
}\r
\r
\r
VOID\r
MiscInitialization (\r
+ VOID\r
)\r
{\r
+ UINTN PmCmd;\r
+ UINTN Pmba;\r
+ UINTN AcpiCtlReg;\r
+ UINT8 AcpiEnBit;\r
+\r
//\r
// Disable A20 Mask\r
//\r
IoOr8 (0x92, BIT1);\r
\r
//\r
- // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
+ // S3 resume as well, so we build it unconditionally.)\r
+ //\r
+ BuildCpuHob (mPhysMemAddressWidth, 16);\r
+\r
+ //\r
+ // Determine platform type and save Host Bridge DID to PCD\r
//\r
- BuildCpuHob (36, 16);\r
+ switch (mHostBridgeDevId) {\r
+ case INTEL_82441_DEVICE_ID:\r
+ PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
+ break;\r
+ case INTEL_Q35_MCH_DEVICE_ID:\r
+ PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
+ break;\r
+ default:\r
+ DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+ __FUNCTION__, mHostBridgeDevId));\r
+ ASSERT (FALSE);\r
+ return;\r
+ }\r
+ PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
\r
//\r
- // Set the PM I/O base address to 0x400\r
+ // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
+ // has been configured (e.g., by Xen) and skip the setup here.\r
+ // This matches the logic in AcpiTimerLibConstructor ().\r
//\r
- PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);\r
+ if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
+ //\r
+ // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
+ // 1. set PMBA\r
+ //\r
+ PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
+\r
+ //\r
+ // 2. set PCICMD/IOSE\r
+ //\r
+ PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
+\r
+ //\r
+ // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
+ //\r
+ PciOr8 (AcpiCtlReg, AcpiEnBit);\r
+ }\r
+\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ //\r
+ // Set Root Complex Register Block BAR\r
+ //\r
+ PciWrite32 (\r
+ POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
+ ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
+ );\r
+ }\r
+}\r
+\r
+\r
+VOID\r
+BootModeInitialization (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ if (CmosRead8 (0xF) == 0xFE) {\r
+ mBootMode = BOOT_ON_S3_RESUME;\r
+ }\r
+\r
+ Status = PeiServicesSetBootMode (mBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = PeiServicesInstallPpi (mPpiBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
//\r
VariableStore =\r
(EFI_PHYSICAL_ADDRESS)(UINTN)\r
- AllocateRuntimePool (\r
- 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
+ AllocateAlignedRuntimePages (\r
+ EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
);\r
DEBUG ((EFI_D_INFO,\r
"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
}\r
\r
\r
+VOID\r
+DebugDumpCmos (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 Loop;\r
+\r
+ DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
+\r
+ for (Loop = 0; Loop < 0x80; Loop++) {\r
+ if ((Loop % 0x10) == 0) {\r
+ DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
+ }\r
+ DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
+ if ((Loop % 0x10) == 0xf) {\r
+ DEBUG ((EFI_D_INFO, "\n"));\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ Set the SMBIOS entry point version for the generic SmbiosDxe driver.\r
+**/\r
+STATIC\r
+VOID\r
+SmbiosVersionInitialization (\r
+ VOID\r
+ )\r
+{\r
+ FIRMWARE_CONFIG_ITEM Anchor;\r
+ UINTN AnchorSize;\r
+ SMBIOS_TABLE_ENTRY_POINT QemuAnchor;\r
+ UINT16 SmbiosVersion;\r
+\r
+ if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,\r
+ &AnchorSize)) ||\r
+ AnchorSize != sizeof QemuAnchor) {\r
+ return;\r
+ }\r
+\r
+ QemuFwCfgSelectItem (Anchor);\r
+ QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);\r
+ if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 ||\r
+ CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {\r
+ return;\r
+ }\r
+\r
+ SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 |\r
+ QemuAnchor.MinorVersion);\r
+ DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,\r
+ SmbiosVersion));\r
+ PcdSet16 (PcdSmbiosVersion, SmbiosVersion);\r
+}\r
+\r
+\r
/**\r
Perform Platform PEI initialization.\r
\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- EFI_PHYSICAL_ADDRESS TopOfMemory;\r
-\r
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
- TopOfMemory = MemDetect ();\r
+ DebugDumpCmos ();\r
+\r
+ XenDetect ();\r
+\r
+ if (QemuFwCfgS3Enabled ()) {\r
+ DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
+ mS3Supported = TRUE;\r
+ }\r
+\r
+ BootModeInitialization ();\r
+ AddressWidthInitialization ();\r
+\r
+ PublishPeiMemory ();\r
+\r
+ InitializeRamRegions ();\r
\r
- ReserveEmuVariableNvStore ();\r
+ if (mXen) {\r
+ DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
+ InitializeXen ();\r
+ }\r
+\r
+ //\r
+ // Query Host Bridge DID\r
+ //\r
+ mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
- PeiFvInitialization ();\r
+ if (mBootMode != BOOT_ON_S3_RESUME) {\r
+ ReserveEmuVariableNvStore ();\r
\r
- MemMapInitialization (TopOfMemory);\r
+ PeiFvInitialization ();\r
+\r
+ MemMapInitialization ();\r
+\r
+ SmbiosVersionInitialization ();\r
+ }\r
\r
MiscInitialization ();\r
\r
projects / mirror_edk2.git / blobdiff