OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 77a8a16c15b8b58485d9b0307732dfad26769613..c064b4ed9b8fb5e85ef3c9805a4dc4bcb40e1544 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -4,13 +4,7 @@
   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
 \r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -180,24 +174,23 @@ MemMapInitialization (
   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
 \r
   if (!mXen) {\r
-    UINT32  TopOfLowRam;\r
     UINT64  PciExBarBase;\r
     UINT32  PciBase;\r
     UINT32  PciSize;\r
 \r
-    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
     PciExBarBase = 0;\r
+    PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base;\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
       //\r
-      // The MMCONFIG area is expected to fall between the top of low RAM and\r
-      // the base of the 32-bit PCI host aperture.\r
+      // The 32-bit PCI host aperture is expected to fall between the top of\r
+      // low RAM and the base of the MMCONFIG area.\r
       //\r
       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
-      ASSERT (TopOfLowRam <= PciExBarBase);\r
+      ASSERT (PciBase < PciExBarBase);\r
       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
-      PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
+      PciSize = (UINT32)(PciExBarBase - PciBase);\r
     } else {\r
-      PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
+      PciSize = 0xFC000000 - PciBase;\r
     }\r
 \r
     //\r
@@ -213,7 +206,6 @@ MemMapInitialization (
     // 0xFED20000    gap                          896 KB\r
     // 0xFEE00000    LAPIC                          1 MB\r
     //\r
-    PciSize = 0xFC000000 - PciBase;\r
     AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
     ASSERT_RETURN_ERROR (PcdStatus);\r
@@ -513,9 +505,8 @@ ReserveEmuVariableNvStore (
   //\r
   VariableStore =\r
     (EFI_PHYSICAL_ADDRESS)(UINTN)\r
-      AllocateAlignedRuntimePages (\r
-        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
-        PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
+      AllocateRuntimePages (\r
+        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
         );\r
   DEBUG ((EFI_D_INFO,\r
           "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
@@ -628,7 +619,7 @@ InitializePlatform (
 {\r
   EFI_STATUS    Status;\r
 \r
-  DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
+  DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
 \r
   DebugDumpCmos ();\r
 \r
@@ -646,6 +637,15 @@ InitializePlatform (
   AddressWidthInitialization ();\r
   MaxCpuCountInitialization ();\r
 \r
+  //\r
+  // Query Host Bridge DID\r
+  //\r
+  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+\r
+  if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
+    Q35TsegMbytesInitialization ();\r
+  }\r
+\r
   PublishPeiMemory ();\r
 \r
   InitializeRamRegions ();\r
@@ -655,18 +655,17 @@ InitializePlatform (
     InitializeXen ();\r
   }\r
 \r
-  //\r
-  // Query Host Bridge DID\r
-  //\r
-  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
-\r
   if (mBootMode != BOOT_ON_S3_RESUME) {\r
-    ReserveEmuVariableNvStore ();\r
+    if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
+      ReserveEmuVariableNvStore ();\r
+    }\r
     PeiFvInitialization ();\r
     MemMapInitialization ();\r
     NoexecDxeInitialization ();\r
   }\r
 \r
+  InstallClearCacheCallback ();\r
+  AmdSevInitialize ();\r
   MiscInitialization ();\r
   InstallFeatureControlCallback ();\r
 \r