OvmfPkg: enable PIIX4 IO space in the PEI phase

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 589c5c3804f27d61a8e1842d7bb71f257b5465fd..ce149e4f979e2c6589fa383ebc2b4232e9df99dc 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -33,6 +33,7 @@
 #include <Library/ResourcePublicationLib.h>\r
 #include <Guid/MemoryTypeInformation.h>\r
 #include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/Pci22.h>\r
 \r
 #include "Platform.h"\r
 #include "Cmos.h"\r
@@ -228,9 +229,27 @@ MiscInitialization (
 \r
   if (!Xen) {\r
     //\r
-    // Set the PM I/O base address to 0x400\r
+    // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+    // 1. set PMBA\r
     //\r
-    PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xFFC0, 0x400);\r
+    PciAndThenOr32 (\r
+      PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
+      (UINT32) ~0xFFC0,\r
+      PcdGet16 (PcdAcpiPmBaseAddress)\r
+      );\r
+\r
+    //\r
+    // 2. set PCICMD/IOSE\r
+    //\r
+    PciOr8 (\r
+      PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
+      EFI_PCI_COMMAND_IO_SPACE\r
+      );\r
+\r
+    //\r
+    // 3. set PMREGMISC/PMIOSE\r
+    //\r
+    PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
   }\r
 }\r
 \r