OvmfPkg/PlatformPei: detect SMRAM at default SMBASE (for real)

[mirror_edk2.git] / OvmfPkg / PlatformPei / PlatformPei.inf

diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf
index 8742008c0d409c1f9b7b84920a8b43f936bd1159..c51a6176aa2e3693b8d6a42cb8852f08187f2505 100644 (file)
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -2,15 +2,9 @@
 #  Platform PEI driver\r
 #\r
 #  This module provides platform specific function to detect boot mode.\r
-#  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+#  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
 #\r
-#  This program and the accompanying materials\r
-#  are licensed and made available under the terms and conditions of the BSD License\r
-#  which accompanies this distribution. The full text of the license may be found at\r
-#  http://opensource.org/licenses/bsd-license.php\r
-#\r
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
 ##\r
 \r
@@ -25,19 +19,26 @@
 #\r
 # The following information is for reference only and not required by the build tools.\r
 #\r
-#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#  VALID_ARCHITECTURES           = IA32 X64 EBC\r
 #\r
 \r
 [Sources]\r
+  AmdSev.c\r
+  ClearCache.c\r
   Cmos.c\r
+  Cmos.h\r
+  FeatureControl.c\r
   Fv.c\r
   MemDetect.c\r
   Platform.c\r
+  Platform.h\r
   Xen.c\r
+  Xen.h\r
 \r
 [Packages]\r
   MdePkg/MdePkg.dec\r
   MdeModulePkg/MdeModulePkg.dec\r
+  SecurityPkg/SecurityPkg.dec\r
   UefiCpuPkg/UefiCpuPkg.dec\r
   OvmfPkg/OvmfPkg.dec\r
 \r
@@ -46,28 +47,71 @@
   gEfiXenInfoGuid\r
 \r
 [LibraryClasses]\r
+  BaseLib\r
+  CacheMaintenanceLib\r
   DebugLib\r
   HobLib\r
   IoLib\r
   PciLib\r
-  PeiResourcePublicationLib\r
+  ResourcePublicationLib\r
   PeiServicesLib\r
   PeiServicesTablePointerLib\r
   PeimEntryPoint\r
+  QemuFwCfgLib\r
+  QemuFwCfgS3Lib\r
   MtrrLib\r
+  MemEncryptSevLib\r
   PcdLib\r
 \r
 [Pcd]\r
-  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfMemFvBase\r
-  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfMemFvSize\r
-  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase\r
+  gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask\r
+  gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize\r
+\r
+[FixedPcd]\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+\r
+[FeaturePcd]\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire\r
 \r
 [Ppis]\r
   gEfiPeiMasterBootModePpiGuid\r
+  gEfiPeiMpServicesPpiGuid\r
 \r
 [Depex]\r
   TRUE\r