EFI_STATUS\r
EFIAPI\r
SmmAccessPeiOpen (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_SMM_ACCESS_PPI *This,\r
- IN UINTN DescriptorIndex\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_SMM_ACCESS_PPI *This,\r
+ IN UINTN DescriptorIndex\r
)\r
{\r
if (DescriptorIndex >= DescIdxCount) {\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiClose (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_SMM_ACCESS_PPI *This,\r
- IN UINTN DescriptorIndex\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_SMM_ACCESS_PPI *This,\r
+ IN UINTN DescriptorIndex\r
)\r
{\r
if (DescriptorIndex >= DescIdxCount) {\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiLock (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_SMM_ACCESS_PPI *This,\r
- IN UINTN DescriptorIndex\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_SMM_ACCESS_PPI *This,\r
+ IN UINTN DescriptorIndex\r
)\r
{\r
if (DescriptorIndex >= DescIdxCount) {\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiGetCapabilities (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_SMM_ACCESS_PPI *This,\r
- IN OUT UINTN *SmramMapSize,\r
- IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_SMM_ACCESS_PPI *This,\r
+ IN OUT UINTN *SmramMapSize,\r
+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap\r
)\r
{\r
- return SmramAccessGetCapabilities (This->LockState, This->OpenState,\r
- SmramMapSize, SmramMap);\r
+ return SmramAccessGetCapabilities (\r
+ This->LockState,\r
+ This->OpenState,\r
+ SmramMapSize,\r
+ SmramMap\r
+ );\r
}\r
\r
//\r
// LockState and OpenState will be filled in by the entry point.\r
//\r
-STATIC PEI_SMM_ACCESS_PPI mAccess = {\r
+STATIC PEI_SMM_ACCESS_PPI mAccess = {\r
&SmmAccessPeiOpen,\r
&SmmAccessPeiClose,\r
&SmmAccessPeiLock,\r
&SmmAccessPeiGetCapabilities\r
};\r
\r
-\r
-STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r
+STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r
{\r
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
&gPeiSmmAccessPpiGuid, &mAccess\r
}\r
};\r
\r
-\r
//\r
// Utility functions.\r
//\r
STATIC\r
UINT8\r
CmosRead8 (\r
- IN UINT8 Index\r
+ IN UINT8 Index\r
)\r
{\r
IoWrite8 (0x70, Index);\r
VOID\r
)\r
{\r
- UINT32 Cmos0x34;\r
- UINT32 Cmos0x35;\r
+ UINT32 Cmos0x34;\r
+ UINT32 Cmos0x35;\r
\r
Cmos0x34 = CmosRead8 (0x34);\r
Cmos0x35 = CmosRead8 (0x35);\r
return ((Cmos0x35 << 8 | Cmos0x34) << 16) + SIZE_16MB;\r
}\r
\r
-\r
//\r
// Entry point of this driver.\r
//\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- UINT16 HostBridgeDevId;\r
- UINT8 EsmramcVal;\r
- UINT8 RegMask8;\r
- UINT32 TopOfLowRam, TopOfLowRamMb;\r
- EFI_STATUS Status;\r
- UINTN SmramMapSize;\r
- EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];\r
- VOID *GuidHob;\r
+ UINT16 HostBridgeDevId;\r
+ UINT8 EsmramcVal;\r
+ UINT8 RegMask8;\r
+ UINT32 TopOfLowRam, TopOfLowRamMb;\r
+ EFI_STATUS Status;\r
+ UINTN SmramMapSize;\r
+ EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];\r
+ VOID *GuidHob;\r
\r
//\r
// This module should only be included if SMRAM support is required.\r
//\r
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
- DEBUG ((DEBUG_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "\r
- "DID=0x%04x (Q35) is supported\n", __FUNCTION__, HostBridgeDevId,\r
- INTEL_Q35_MCH_DEVICE_ID));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: no SMRAM with host bridge DID=0x%04x; only "\r
+ "DID=0x%04x (Q35) is supported\n",\r
+ __FUNCTION__,\r
+ HostBridgeDevId,\r
+ INTEL_Q35_MCH_DEVICE_ID\r
+ ));\r
goto WrongConfig;\r
}\r
\r
// bits are hard-coded as 1 by QEMU.\r
//\r
EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));\r
- RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;\r
+ RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;\r
if ((EsmramcVal & RegMask8) != RegMask8) {\r
- DEBUG ((DEBUG_ERROR, "%a: this Q35 implementation lacks SMRAM\n",\r
- __FUNCTION__));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: this Q35 implementation lacks SMRAM\n",\r
+ __FUNCTION__\r
+ ));\r
goto WrongConfig;\r
}\r
\r
//\r
// Set Top of Low Usable DRAM.\r
//\r
- PciWrite16 (DRAMC_REGISTER_Q35 (MCH_TOLUD),\r
- (UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT));\r
+ PciWrite16 (\r
+ DRAMC_REGISTER_Q35 (MCH_TOLUD),\r
+ (UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT)\r
+ );\r
\r
//\r
// Given the zero graphics memory sizes configured above, set the\r
// graphics-related stolen memory bases to the same as TOLUD.\r
//\r
- PciWrite32 (DRAMC_REGISTER_Q35 (MCH_GBSM),\r
- TopOfLowRamMb << MCH_GBSM_MB_SHIFT);\r
- PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM),\r
- TopOfLowRamMb << MCH_BGSM_MB_SHIFT);\r
+ PciWrite32 (\r
+ DRAMC_REGISTER_Q35 (MCH_GBSM),\r
+ TopOfLowRamMb << MCH_GBSM_MB_SHIFT\r
+ );\r
+ PciWrite32 (\r
+ DRAMC_REGISTER_Q35 (MCH_BGSM),\r
+ TopOfLowRamMb << MCH_BGSM_MB_SHIFT\r
+ );\r
\r
//\r
// Set TSEG Memory Base.\r
//\r
InitQ35TsegMbytes ();\r
- PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB),\r
- (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT);\r
+ PciWrite32 (\r
+ DRAMC_REGISTER_Q35 (MCH_TSEGMB),\r
+ (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT\r
+ );\r
\r
//\r
// Set TSEG size, and disable TSEG visibility outside of SMM. Note that the\r
// TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME\r
// (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.\r
//\r
- PciAndThenOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM),\r
- (UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff), MCH_SMRAM_G_SMRAME);\r
+ PciAndThenOr8 (\r
+ DRAMC_REGISTER_Q35 (MCH_SMRAM),\r
+ (UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff),\r
+ MCH_SMRAM_G_SMRAME\r
+ );\r
\r
//\r
// Create the GUID HOB and point it to the first SMRAM range.\r
//\r
GetStates (&mAccess.LockState, &mAccess.OpenState);\r
SmramMapSize = sizeof SmramMap;\r
- Status = SmramAccessGetCapabilities (mAccess.LockState, mAccess.OpenState,\r
- &SmramMapSize, SmramMap);\r
+ Status = SmramAccessGetCapabilities (\r
+ mAccess.LockState,\r
+ mAccess.OpenState,\r
+ &SmramMapSize,\r
+ SmramMap\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
\r
DEBUG_CODE_BEGIN ();\r
{\r
- UINTN Count;\r
- UINTN Idx;\r
+ UINTN Count;\r
+ UINTN Idx;\r
\r
Count = SmramMapSize / sizeof SmramMap[0];\r
- DEBUG ((DEBUG_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,\r
- (INT32)Count));\r
- DEBUG ((DEBUG_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",\r
- "PhysicalSize(0x)", "CpuStart(0x)", "RegionState(0x)"));\r
+ DEBUG ((\r
+ DEBUG_VERBOSE,\r
+ "%a: SMRAM map follows, %d entries\n",\r
+ __FUNCTION__,\r
+ (INT32)Count\r
+ ));\r
+ DEBUG ((\r
+ DEBUG_VERBOSE,\r
+ "% 20a % 20a % 20a % 20a\n",\r
+ "PhysicalStart(0x)",\r
+ "PhysicalSize(0x)",\r
+ "CpuStart(0x)",\r
+ "RegionState(0x)"\r
+ ));\r
for (Idx = 0; Idx < Count; ++Idx) {\r
- DEBUG ((DEBUG_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
- SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize,\r
- SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState));\r
+ DEBUG ((\r
+ DEBUG_VERBOSE,\r
+ "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
+ SmramMap[Idx].PhysicalStart,\r
+ SmramMap[Idx].PhysicalSize,\r
+ SmramMap[Idx].CpuStart,\r
+ SmramMap[Idx].RegionState\r
+ ));\r
}\r
}\r
DEBUG_CODE_END ();\r
\r
- GuidHob = BuildGuidHob (&gEfiAcpiVariableGuid,\r
- sizeof SmramMap[DescIdxSmmS3ResumeState]);\r
+ GuidHob = BuildGuidHob (\r
+ &gEfiAcpiVariableGuid,\r
+ sizeof SmramMap[DescIdxSmmS3ResumeState]\r
+ );\r
if (GuidHob == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- CopyMem (GuidHob, &SmramMap[DescIdxSmmS3ResumeState],\r
- sizeof SmramMap[DescIdxSmmS3ResumeState]);\r
+ CopyMem (\r
+ GuidHob,\r
+ &SmramMap[DescIdxSmmS3ResumeState],\r
+ sizeof SmramMap[DescIdxSmmS3ResumeState]\r
+ );\r
\r
//\r
// SmramAccessLock() depends on "mQ35SmramAtDefaultSmbase"; init the latter\r
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