VOID\r
EFIAPI\r
OnS3SaveStateInstalled (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
);\r
\r
//\r
// S3SaveState protocol installation callback, strictly before the runtime\r
// phase.\r
//\r
-STATIC UINTN mSmiEnable;\r
+STATIC UINTN mSmiEnable;\r
\r
//\r
// Captures whether SMI feature negotiation is supported. The variable is only\r
// used to carry this information from the entry point function to the\r
// S3SaveState protocol installation callback.\r
//\r
-STATIC BOOLEAN mSmiFeatureNegotiation;\r
+STATIC BOOLEAN mSmiFeatureNegotiation;\r
\r
//\r
// Event signaled when an S3SaveState protocol interface is installed.\r
//\r
-STATIC EFI_EVENT mS3SaveStateInstalled;\r
+STATIC EFI_EVENT mS3SaveStateInstalled;\r
\r
/**\r
Invokes SMI activation from either the preboot or runtime environment.\r
//\r
// No support for queued or periodic activation.\r
//\r
- if (Periodic || ActivationInterval > 0) {\r
+ if (Periodic || (ActivationInterval > 0)) {\r
return EFI_DEVICE_ERROR;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
\r
-STATIC EFI_SMM_CONTROL2_PROTOCOL mControl2 = {\r
+STATIC EFI_SMM_CONTROL2_PROTOCOL mControl2 = {\r
&SmmControl2DxeTrigger,\r
&SmmControl2DxeClear,\r
MAX_UINTN // MinimumTriggerPeriod -- we don't support periodic SMIs\r
EFI_STATUS\r
EFIAPI\r
SmmControl2DxeEntryPoint (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- UINT32 PmBase;\r
- UINT32 SmiEnableVal;\r
- EFI_STATUS Status;\r
+ UINT32 PmBase;\r
+ UINT32 SmiEnableVal;\r
+ EFI_STATUS Status;\r
\r
//\r
// This module should only be included if SMRAM support is required.\r
// ACPI PM IO space.)\r
//\r
PmBase = PciRead32 (POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE)) &\r
- ICH9_PMBASE_MASK;\r
+ ICH9_PMBASE_MASK;\r
mSmiEnable = PmBase + ICH9_PMBASE_OFS_SMI_EN;\r
\r
//\r
//\r
SmiEnableVal = IoRead32 (mSmiEnable);\r
if ((SmiEnableVal & ICH9_SMI_EN_APMC_EN) != 0) {\r
- DEBUG ((DEBUG_ERROR, "%a: this Q35 implementation lacks SMI\n",\r
- __FUNCTION__));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: this Q35 implementation lacks SMI\n",\r
+ __FUNCTION__\r
+ ));\r
goto FatalError;\r
}\r
\r
//\r
// Prevent software from undoing the above (until platform reset).\r
//\r
- PciOr16 (POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),\r
- ICH9_GEN_PMCON_1_SMI_LOCK);\r
+ PciOr16 (\r
+ POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),\r
+ ICH9_GEN_PMCON_1_SMI_LOCK\r
+ );\r
\r
//\r
// If we can clear GBL_SMI_EN now, that means QEMU's SMI support is not\r
//\r
IoWrite32 (mSmiEnable, SmiEnableVal & ~(UINT32)ICH9_SMI_EN_GBL_SMI_EN);\r
if (IoRead32 (mSmiEnable) != SmiEnableVal) {\r
- DEBUG ((DEBUG_ERROR, "%a: failed to lock down GBL_SMI_EN\n",\r
- __FUNCTION__));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: failed to lock down GBL_SMI_EN\n",\r
+ __FUNCTION__\r
+ ));\r
goto FatalError;\r
}\r
\r
mSmiFeatureNegotiation = NegotiateSmiFeatures ();\r
\r
if (PcdGetBool (PcdAcpiS3Enable)) {\r
- VOID *Registration;\r
+ VOID *Registration;\r
\r
//\r
// On S3 resume the above register settings have to be repeated. Register a\r
// protocol notify callback that, when boot script saving becomes\r
// available, saves operations equivalent to the above to the boot script.\r
//\r
- Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,\r
- OnS3SaveStateInstalled, NULL /* Context */,\r
- &mS3SaveStateInstalled);\r
+ Status = gBS->CreateEvent (\r
+ EVT_NOTIFY_SIGNAL,\r
+ TPL_CALLBACK,\r
+ OnS3SaveStateInstalled,\r
+ NULL /* Context */,\r
+ &mS3SaveStateInstalled\r
+ );\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "%a: CreateEvent: %r\n", __FUNCTION__, Status));\r
goto FatalError;\r
}\r
\r
- Status = gBS->RegisterProtocolNotify (&gEfiS3SaveStateProtocolGuid,\r
- mS3SaveStateInstalled, &Registration);\r
+ Status = gBS->RegisterProtocolNotify (\r
+ &gEfiS3SaveStateProtocolGuid,\r
+ mS3SaveStateInstalled,\r
+ &Registration\r
+ );\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: RegisterProtocolNotify: %r\n", __FUNCTION__,\r
- Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: RegisterProtocolNotify: %r\n",\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
goto ReleaseEvent;\r
}\r
\r
// We have no pointers to convert to virtual addresses. The handle itself\r
// doesn't matter, as protocol services are not accessible at runtime.\r
//\r
- Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,\r
- &gEfiSmmControl2ProtocolGuid, &mControl2,\r
- NULL);\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &ImageHandle,\r
+ &gEfiSmmControl2ProtocolGuid,\r
+ &mControl2,\r
+ NULL\r
+ );\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: InstallMultipleProtocolInterfaces: %r\n",\r
- __FUNCTION__, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: InstallMultipleProtocolInterfaces: %r\n",\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
goto ReleaseEvent;\r
}\r
\r
VOID\r
EFIAPI\r
OnS3SaveStateInstalled (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState;\r
- UINT32 SmiEnOrMask, SmiEnAndMask;\r
- UINT64 GenPmCon1Address;\r
- UINT16 GenPmCon1OrMask, GenPmCon1AndMask;\r
+ EFI_STATUS Status;\r
+ EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState;\r
+ UINT32 SmiEnOrMask, SmiEnAndMask;\r
+ UINT64 GenPmCon1Address;\r
+ UINT16 GenPmCon1OrMask, GenPmCon1AndMask;\r
\r
ASSERT (Event == mS3SaveStateInstalled);\r
\r
- Status = gBS->LocateProtocol (&gEfiS3SaveStateProtocolGuid,\r
- NULL /* Registration */, (VOID **)&S3SaveState);\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiS3SaveStateProtocolGuid,\r
+ NULL /* Registration */,\r
+ (VOID **)&S3SaveState\r
+ );\r
if (EFI_ERROR (Status)) {\r
return;\r
}\r
//\r
SmiEnOrMask = ICH9_SMI_EN_APMC_EN | ICH9_SMI_EN_GBL_SMI_EN;\r
SmiEnAndMask = MAX_UINT32;\r
- Status = S3SaveState->Write (\r
- S3SaveState,\r
- EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE,\r
- EfiBootScriptWidthUint32,\r
- (UINT64)mSmiEnable,\r
- &SmiEnOrMask,\r
- &SmiEnAndMask\r
- );\r
+ Status = S3SaveState->Write (\r
+ S3SaveState,\r
+ EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE,\r
+ EfiBootScriptWidthUint32,\r
+ (UINT64)mSmiEnable,\r
+ &SmiEnOrMask,\r
+ &SmiEnAndMask\r
+ );\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE: %r\n",\r
- __FUNCTION__, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE: %r\n",\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
ASSERT (FALSE);\r
CpuDeadLoop ();\r
}\r
\r
GenPmCon1Address = POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS (\r
- ICH9_GEN_PMCON_1);\r
+ ICH9_GEN_PMCON_1\r
+ );\r
GenPmCon1OrMask = ICH9_GEN_PMCON_1_SMI_LOCK;\r
GenPmCon1AndMask = MAX_UINT16;\r
- Status = S3SaveState->Write (\r
- S3SaveState,\r
- EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE,\r
- EfiBootScriptWidthUint16,\r
- GenPmCon1Address,\r
- &GenPmCon1OrMask,\r
- &GenPmCon1AndMask\r
- );\r
+ Status = S3SaveState->Write (\r
+ S3SaveState,\r
+ EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE,\r
+ EfiBootScriptWidthUint16,\r
+ GenPmCon1Address,\r
+ &GenPmCon1OrMask,\r
+ &GenPmCon1AndMask\r
+ );\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR,\r
- "%a: EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE: %r\n", __FUNCTION__,\r
- Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE: %r\n",\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
ASSERT (FALSE);\r
CpuDeadLoop ();\r
}\r
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