#include "Platform.h"\r
#include "Cmos.h"\r
\r
-UINT8 mPhysMemAddressWidth;\r
+UINT8 mPhysMemAddressWidth;\r
\r
-STATIC UINT32 mS3AcpiReservedMemoryBase;\r
-STATIC UINT32 mS3AcpiReservedMemorySize;\r
+STATIC UINT32 mS3AcpiReservedMemoryBase;\r
+STATIC UINT32 mS3AcpiReservedMemorySize;\r
\r
-STATIC UINT16 mQ35TsegMbytes;\r
+STATIC UINT16 mQ35TsegMbytes;\r
\r
VOID\r
Q35TsegMbytesInitialization (\r
VOID\r
)\r
{\r
- UINT16 ExtendedTsegMbytes;\r
- RETURN_STATUS PcdStatus;\r
+ UINT16 ExtendedTsegMbytes;\r
+ RETURN_STATUS PcdStatus;\r
\r
if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
DEBUG ((\r
STATIC\r
UINT64\r
GetHighestSystemMemoryAddress (\r
- BOOLEAN Below4gb\r
+ BOOLEAN Below4gb\r
)\r
{\r
- EFI_E820_ENTRY64 *E820Map;\r
- UINT32 E820EntriesCount;\r
- EFI_E820_ENTRY64 *Entry;\r
- EFI_STATUS Status;\r
- UINT32 Loop;\r
- UINT64 HighestAddress;\r
- UINT64 EntryEnd;\r
+ EFI_E820_ENTRY64 *E820Map;\r
+ UINT32 E820EntriesCount;\r
+ EFI_E820_ENTRY64 *Entry;\r
+ EFI_STATUS Status;\r
+ UINT32 Loop;\r
+ UINT64 HighestAddress;\r
+ UINT64 EntryEnd;\r
\r
HighestAddress = 0;\r
\r
ASSERT_EFI_ERROR (Status);\r
\r
for (Loop = 0; Loop < E820EntriesCount; Loop++) {\r
- Entry = E820Map + Loop;\r
+ Entry = E820Map + Loop;\r
EntryEnd = Entry->BaseAddr + Entry->Length;\r
\r
- if (Entry->Type == EfiAcpiAddressRangeMemory &&\r
- EntryEnd > HighestAddress) {\r
-\r
+ if ((Entry->Type == EfiAcpiAddressRangeMemory) &&\r
+ (EntryEnd > HighestAddress))\r
+ {\r
if (Below4gb && (EntryEnd <= BASE_4GB)) {\r
HighestAddress = EntryEnd;\r
} else if (!Below4gb && (EntryEnd >= BASE_4GB)) {\r
VOID\r
)\r
{\r
- UINT8 Cmos0x34;\r
- UINT8 Cmos0x35;\r
+ UINT8 Cmos0x34;\r
+ UINT8 Cmos0x35;\r
\r
//\r
// In PVH case, there is no CMOS, we have to calculate the memory size\r
// into the calculation to get the total memory size.\r
//\r
\r
- Cmos0x34 = (UINT8) CmosRead8 (0x34);\r
- Cmos0x35 = (UINT8) CmosRead8 (0x35);\r
+ Cmos0x34 = (UINT8)CmosRead8 (0x34);\r
+ Cmos0x35 = (UINT8)CmosRead8 (0x35);\r
\r
- return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
+ return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- UINT32 RegEax;\r
+ UINT32 RegEax;\r
\r
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
if (RegEax >= 0x80000008) {\r
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
- mPhysMemAddressWidth = (UINT8) RegEax;\r
+ mPhysMemAddressWidth = (UINT8)RegEax;\r
} else {\r
mPhysMemAddressWidth = 36;\r
}\r
VOID\r
)\r
{\r
- BOOLEAN Page1GSupport;\r
- UINT32 RegEax;\r
- UINT32 RegEdx;\r
- UINT32 Pml4Entries;\r
- UINT32 PdpEntries;\r
- UINTN TotalPages;\r
+ BOOLEAN Page1GSupport;\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ UINT32 Pml4Entries;\r
+ UINT32 PdpEntries;\r
+ UINTN TotalPages;\r
\r
//\r
// If DXE is 32-bit, then just return the traditional 64 MB cap.\r
//\r
-#ifdef MDE_CPU_IA32\r
+ #ifdef MDE_CPU_IA32\r
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
return SIZE_64MB;\r
}\r
-#endif\r
+\r
+ #endif\r
\r
//\r
// Dependent on physical address width, PEI memory allocations can be\r
\r
if (mPhysMemAddressWidth <= 39) {\r
Pml4Entries = 1;\r
- PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
+ PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
ASSERT (PdpEntries <= 0x200);\r
} else {\r
Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r
}\r
\r
TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
- (PdpEntries + 1) * Pml4Entries + 1;\r
+ (PdpEntries + 1) * Pml4Entries + 1;\r
ASSERT (TotalPages <= 0x40201);\r
\r
//\r
return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
}\r
\r
-\r
/**\r
Publish PEI core memory\r
\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS MemoryBase;\r
- UINT64 MemorySize;\r
- UINT32 LowerMemorySize;\r
- UINT32 PeiMemoryCap;\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS MemoryBase;\r
+ UINT64 MemorySize;\r
+ UINT32 LowerMemorySize;\r
+ UINT32 PeiMemoryCap;\r
\r
LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
\r
MemorySize = mS3AcpiReservedMemorySize;\r
} else {\r
PeiMemoryCap = GetPeiMemoryCap ();\r
- DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
- __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
+ __FUNCTION__,\r
+ mPhysMemAddressWidth,\r
+ PeiMemoryCap >> 10\r
+ ));\r
\r
//\r
// Determine the range of memory to use during PEI\r
//\r
// Publish this memory to the PEI Core\r
//\r
- Status = PublishSystemMemory(MemoryBase, MemorySize);\r
+ Status = PublishSystemMemory (MemoryBase, MemorySize);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Publish system RAM and reserve memory regions\r
\r
// such that they would overlap the LockBox storage.\r
//\r
ZeroMem (\r
- (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r
+ (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
+ (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)\r
);\r
BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
+ (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),\r
EfiBootServicesData\r
);\r
}\r