/** @file\r
- Pci Host Bridge driver: \r
- Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation\r
+ Provides the basic interfaces to abstract a PCI Host Bridge Resource\r
+ Allocation\r
\r
- Copyright (c) 2008 - 2009, Intel Corporation<BR> All rights\r
- reserved. This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
+ Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
- \r
+\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
-**/ \r
+**/\r
\r
#include "PciHostBridge.h"\r
\r
-//\r
-// Support 64 K IO space\r
-//\r
-#define RES_IO_BASE 0x1000\r
-#define RES_IO_LIMIT 0xFFFF\r
-//\r
-// Support 4G address space\r
-//\r
-#define RES_MEM_BASE_1 0xF8000000\r
-#define RES_MEM_LIMIT_1 (0xFEC00000 - 1)\r
-\r
//\r
// Hard code: Root Bridge Number within the host bridge\r
// Root Bridge's attribute\r
// Root Bridge's device path\r
-// Root Bridge's resource appeture\r
+// Root Bridge's resource aperture\r
//\r
UINTN RootBridgeNumber[1] = { 1 };\r
\r
-UINT64 RootBridgeAttribute[1][1] = { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM };\r
+UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };\r
\r
EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {\r
{\r
- ACPI_DEVICE_PATH,\r
- ACPI_DP,\r
- (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
- (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8),\r
- EISA_PNP_ID(0x0A03),\r
- 0,\r
- END_DEVICE_PATH_TYPE,\r
- END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
- END_DEVICE_PATH_LENGTH,\r
- 0\r
+ {\r
+ {\r
+ {\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_DP,\r
+ {\r
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ EISA_PNP_ID(0x0A03),\r
+ 0\r
+ },\r
+ \r
+ {\r
+ END_DEVICE_PATH_TYPE,\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ {\r
+ END_DEVICE_PATH_LENGTH,\r
+ 0\r
+ }\r
+ }\r
+ }\r
}\r
};\r
\r
-PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[1][1] = {\r
- {0, 0, 0, 0xffffffff, 0, 1 << 16}\r
+PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1] = {\r
+ {{0, 0xff, 0x80000000, 0xffffffff, 0, 0xffff}}\r
};\r
\r
EFI_HANDLE mDriverImageHandle;\r
//\r
// Implementation\r
//\r
+\r
+/**\r
+ Entry point of this driver\r
+\r
+ @param ImageHandle Handle of driver image\r
+ @param SystemTable Point to EFI_SYSTEM_TABLE\r
+\r
+ @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource\r
+ @retval EFI_DEVICE_ERROR Can not install the protocol instance\r
+ @retval EFI_SUCCESS Success to initialize the Pci host bridge.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
InitializePciHostBridge (\r
IN EFI_HANDLE ImageHandle,\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
-/*++\r
-\r
-Routine Description:\r
- Entry point of this driver\r
-\r
-Arguments:\r
-\r
- ImageHandle -\r
-\r
- SystemTable -\r
- \r
-Returns:\r
-\r
---*/\r
{\r
EFI_STATUS Status;\r
UINTN Loop1;\r
UINTN Loop2;\r
PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress;\r
- IN UINT64 Length;\r
\r
mDriverImageHandle = ImageHandle;\r
\r
&PrivateData->Io, \r
HostBridge->HostBridgeHandle, \r
RootBridgeAttribute[Loop1][Loop2], \r
- &mResAppeture[Loop1][Loop2]\r
+ &mResAperture[Loop1][Loop2]\r
);\r
\r
Status = gBS->InstallMultipleProtocolInterfaces(\r
}\r
} \r
\r
- Status = gDS->AddIoSpace (\r
- EfiGcdIoTypeIo, \r
- RES_IO_BASE, \r
- RES_IO_LIMIT - RES_IO_BASE + 1\r
- );\r
- \r
- // PCI memory space from 3.75Gbytes->(4GBytes - BIOSFWH local APIC etc)\r
- Status = gDS->AddMemorySpace (\r
- EfiGcdMemoryTypeMemoryMappedIo, \r
- RES_MEM_BASE_1, \r
- (RES_MEM_LIMIT_1 - RES_MEM_BASE_1 + 1),\r
- 0\r
- );\r
- \r
- BaseAddress = 0x80000000;\r
- Length = RES_MEM_BASE_1 - BaseAddress;\r
- Status = gDS->AddMemorySpace (\r
- EfiGcdMemoryTypeMemoryMappedIo, \r
- BaseAddress, \r
- Length,\r
- 0\r
- );\r
- \r
return EFI_SUCCESS;\r
}\r
\r
\r
+/**\r
+ These are the notifications from the PCI bus driver that it is about to enter\r
+ a certain phase of the PCI enumeration process.\r
+\r
+ This member function can be used to notify the host bridge driver to perform\r
+ specific actions, including any chipset-specific initialization, so that the\r
+ chipset is ready to enter the next phase. Eight notification points are\r
+ defined at this time. See belows:\r
+\r
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures\r
+ and internal data structures. The PCI\r
+ enumerator should issue this\r
+ notification before starting a fresh\r
+ enumeration process. Enumeration\r
+ cannot be restarted after sending any\r
+ other notification such as\r
+ EfiPciHostBridgeBeginBusAllocation.\r
+\r
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to\r
+ begin. No specific action is required\r
+ here. This notification can be used to\r
+ perform any chipset-specific\r
+ programming.\r
+\r
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming\r
+ phase is complete. No specific action\r
+ is required here. This notification\r
+ can be used to perform any\r
+ chipset-specific programming.\r
+\r
+ EfiPciHostBridgeBeginResourceAllocation\r
+ The resource allocation phase is about\r
+ to begin. No specific action is\r
+ required here. This notification can\r
+ be used to perform any\r
+ chipset-specific programming.\r
+\r
+ EfiPciHostBridgeAllocateResources Allocates resources per previously\r
+ submitted requests for all the PCI\r
+ root bridges. These resource settings\r
+ are returned on the next call to\r
+ GetProposedResources(). Before calling\r
+ NotifyPhase() with a Phase of\r
+ EfiPciHostBridgeAllocateResource, the\r
+ PCI bus enumerator is responsible for\r
+ gathering I/O and memory requests for\r
+ all the PCI root bridges and\r
+ submitting these requests using\r
+ SubmitResources(). This function pads\r
+ the resource amount to suit the root\r
+ bridge hardware, takes care of\r
+ dependencies between the PCI root\r
+ bridges, and calls the Global\r
+ Coherency Domain (GCD) with the\r
+ allocation request. In the case of\r
+ padding, the allocated range could be\r
+ bigger than what was requested.\r
+\r
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to\r
+ decode previously allocated resources\r
+ (proposed resources) for all the PCI\r
+ root bridges. After the hardware is\r
+ programmed, reassigning resources will\r
+ not be supported. The bus settings are\r
+ not affected.\r
+\r
+ EfiPciHostBridgeFreeResources Deallocates resources that were\r
+ previously allocated for all the PCI\r
+ root bridges and resets the I/O and\r
+ memory apertures to their initial\r
+ state. The bus settings are not\r
+ affected. If the request to allocate\r
+ resources fails, the PCI enumerator\r
+ can use this notification to\r
+ deallocate previous resources, adjust\r
+ the requests, and retry allocation.\r
+\r
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is\r
+ completed. No specific action is\r
+ required here. This notification can\r
+ be used to perform any chipsetspecific\r
+ programming.\r
+\r
+ @param[in] This The instance pointer of\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+\r
+ @param[in] Phase The phase during enumeration\r
+\r
+ @retval EFI_NOT_READY This phase cannot be entered at this time. For\r
+ example, this error is valid for a Phase of\r
+ EfiPciHostBridgeAllocateResources if\r
+ SubmitResources() has not been called for one\r
+ or more PCI root bridges before this call\r
+\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ This error is valid for a Phase of\r
+ EfiPciHostBridgeSetResources.\r
+\r
+ @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
+\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
+ lack of resources. This error is valid for a\r
+ Phase of EfiPciHostBridgeAllocateResources if\r
+ the previously submitted resource requests\r
+ cannot be fulfilled or were only partially\r
+ fulfilled.\r
+\r
+ @retval EFI_SUCCESS The notification was accepted without any\r
+ errors.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
NotifyPhase(\r
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
)\r
-/*++\r
-\r
-Routine Description:\r
- Enter a certain phase of the PCI enumeration process\r
-\r
-Arguments:\r
- This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance\r
- Phase -- The phase during enumeration\r
- \r
-Returns:\r
-\r
---*/ \r
{\r
PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
} \r
break;\r
\r
+ case EfiPciHostBridgeEndEnumeration:\r
+ break;\r
+\r
case EfiPciHostBridgeBeginBusAllocation:\r
//\r
// No specific action is required here, can perform any chipset specific programing\r
//\r
HostBridgeInstance->CanRestarted = FALSE;\r
- return EFI_SUCCESS;\r
break;\r
\r
case EfiPciHostBridgeEndBusAllocation:\r
// No specific action is required here, can perform any chipset specific programing\r
//\r
//HostBridgeInstance->CanRestarted = FALSE;\r
- return EFI_SUCCESS;\r
break;\r
\r
case EfiPciHostBridgeBeginResourceAllocation:\r
// No specific action is required here, can perform any chipset specific programing\r
//\r
//HostBridgeInstance->CanRestarted = FALSE;\r
- return EFI_SUCCESS;\r
break;\r
\r
case EfiPciHostBridgeAllocateResources:\r
//\r
// Get the number of '1' in Alignment.\r
//\r
- BitsOfAlignment = HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1;\r
+ BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);\r
\r
switch (Index) {\r
\r
HostBridgeInstance->ResourceSubmited = FALSE;\r
HostBridgeInstance->CanRestarted = TRUE; \r
return ReturnStatus;\r
- break;\r
\r
case EfiPciHostBridgeEndResourceAllocation:\r
HostBridgeInstance->CanRestarted = FALSE;\r
\r
default:\r
return EFI_INVALID_PARAMETER;\r
- }; // end switch\r
+ }\r
\r
return EFI_SUCCESS; \r
}\r
\r
+/**\r
+ Return the device handle of the next PCI root bridge that is associated with\r
+ this Host Bridge.\r
+\r
+ This function is called multiple times to retrieve the device handles of all\r
+ the PCI root bridges that are associated with this PCI host bridge. Each PCI\r
+ host bridge is associated with one or more PCI root bridges. On each call,\r
+ the handle that was returned by the previous call is passed into the\r
+ interface, and on output the interface returns the device handle of the next\r
+ PCI root bridge. The caller can use the handle to obtain the instance of the\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no more\r
+ PCI root bridges to report, the interface returns EFI_NOT_FOUND. A PCI\r
+ enumerator must enumerate the PCI root bridges in the order that they are\r
+ returned by this function.\r
+\r
+ For D945 implementation, there is only one root bridge in PCI host bridge.\r
+\r
+ @param[in] This The instance pointer of\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+\r
+ @param[in, out] RootBridgeHandle Returns the device handle of the next PCI\r
+ root bridge.\r
+\r
+ @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then\r
+ return the first Rootbridge handle of the\r
+ specific Host bridge and return EFI_SUCCESS.\r
+\r
+ @retval EFI_NOT_FOUND Can not find the any more root bridge in\r
+ specific host bridge.\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r
+ returned on a previous call to\r
+ GetNextRootBridge().\r
+**/\r
EFI_STATUS\r
EFIAPI\r
GetNextRootBridge(\r
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
IN OUT EFI_HANDLE *RootBridgeHandle\r
)\r
-/*++\r
-\r
-Routine Description:\r
- Return the device handle of the next PCI root bridge that is associated with \r
- this Host Bridge\r
-\r
-Arguments:\r
- This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
- RootBridgeHandle -- Returns the device handle of the next PCI Root Bridge. \r
- On input, it holds the RootBridgeHandle returned by the most \r
- recent call to GetNextRootBridge().The handle for the first \r
- PCI Root Bridge is returned if RootBridgeHandle is NULL on input\r
- \r
-Returns:\r
-\r
---*/ \r
{\r
BOOLEAN NoRootBridge; \r
LIST_ENTRY *List; \r
}\r
}\r
\r
+/**\r
+ Returns the allocation attributes of a PCI root bridge.\r
+\r
+ The function returns the allocation attributes of a specific PCI root bridge.\r
+ The attributes can vary from one PCI root bridge to another. These attributes\r
+ are different from the decode-related attributes that are returned by the\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
+ RootBridgeHandle parameter is used to specify the instance of the PCI root\r
+ bridge. The device handles of all the root bridges that are associated with\r
+ this host bridge must be obtained by calling GetNextRootBridge(). The\r
+ attributes are static in the sense that they do not change during or after\r
+ the enumeration process. The hardware may provide mechanisms to change the\r
+ attributes on the fly, but such changes must be completed before\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is installed. The permitted\r
+ values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
+ "Related Definitions" below. The caller uses these attributes to combine\r
+ multiple resource requests.\r
+\r
+ For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI\r
+ bus enumerator needs to include requests for the prefetchable memory in the\r
+ nonprefetchable memory pool and not request any prefetchable memory.\r
+\r
+ Attribute Description\r
+ ------------------------------------ ---------------------------------------\r
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root\r
+ bridge does not support separate\r
+ windows for nonprefetchable and\r
+ prefetchable memory. A PCI bus driver\r
+ needs to include requests for\r
+ prefetchable memory in the\r
+ nonprefetchable memory pool.\r
+\r
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root\r
+ bridge supports 64-bit memory windows.\r
+ If this bit is not set, the PCI bus\r
+ driver needs to include requests for a\r
+ 64-bit memory address in the\r
+ corresponding 32-bit memory pool.\r
+\r
+ @param[in] This The instance pointer of\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+\r
+ @param[in] RootBridgeHandle The device handle of the PCI root bridge in\r
+ which the caller is interested. Type\r
+ EFI_HANDLE is defined in\r
+ InstallProtocolInterface() in the UEFI 2.0\r
+ Specification.\r
+\r
+ @param[out] Attributes The pointer to attribte of root bridge, it is\r
+ output parameter\r
+\r
+ @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r
+\r
+ @retval EFI_SUCCESS Success to get attribute of interested root\r
+ bridge.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
GetAttributes(\r
IN EFI_HANDLE RootBridgeHandle,\r
OUT UINT64 *Attributes\r
)\r
-/*++\r
-\r
-Routine Description:\r
- Returns the attributes of a PCI Root Bridge.\r
-\r
-Arguments:\r
- This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
- RootBridgeHandle -- The device handle of the PCI Root Bridge \r
- that the caller is interested in\r
- Attribute -- The pointer to attributes of the PCI Root Bridge \r
- \r
-Returns:\r
-\r
---*/ \r
{\r
LIST_ENTRY *List; \r
PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
+/**\r
+ Sets up the specified PCI root bridge for the bus enumeration process.\r
+\r
+ This member function sets up the root bridge for bus enumeration and returns\r
+ the PCI bus range over which the search should be performed in ACPI 2.0\r
+ resource descriptor format.\r
+\r
+ @param[in] This The\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance.\r
+\r
+ @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r
+\r
+ @param[out] Configuration Pointer to the pointer to the PCI bus resource\r
+ descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
+\r
+ @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r
+\r
+ @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
StartBusEnumeration(\r
IN EFI_HANDLE RootBridgeHandle,\r
OUT VOID **Configuration\r
)\r
-/*++\r
-\r
-Routine Description:\r
- This is the request from the PCI enumerator to set up \r
- the specified PCI Root Bridge for bus enumeration process. \r
-\r
-Arguments:\r
- This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
- RootBridgeHandle -- The PCI Root Bridge to be set up\r
- Configuration -- Pointer to the pointer to the PCI bus resource descriptor\r
- \r
-Returns:\r
-\r
---*/\r
{\r
LIST_ENTRY *List; \r
PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
+/**\r
+ Programs the PCI root bridge hardware so that it decodes the specified PCI\r
+ bus range.\r
+\r
+ This member function programs the specified PCI root bridge to decode the bus\r
+ range that is specified by the input parameter Configuration.\r
+ The bus range information is specified in terms of the ACPI 2.0 resource\r
+ descriptor format.\r
+\r
+ @param[in] This The\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance\r
+\r
+ @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be\r
+ programmed\r
+\r
+ @param[in] Configuration The pointer to the PCI bus resource descriptor\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
+ handle.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI\r
+ 2.0 resource descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI\r
+ 2.0 bus resource descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource\r
+ descriptors other than bus descriptors.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid\r
+ ACPI resource descriptors.\r
+\r
+ @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this\r
+ root bridge.\r
+\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this\r
+ root bridge.\r
+\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+\r
+ @retval EFI_SUCCESS The bus range for the PCI root bridge was\r
+ programmed.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
SetBusNumbers(\r
IN EFI_HANDLE RootBridgeHandle,\r
IN VOID *Configuration\r
)\r
-/*++\r
-\r
-Routine Description:\r
- This function programs the PCI Root Bridge hardware so that \r
- it decodes the specified PCI bus range\r
-\r
-Arguments:\r
- This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
- RootBridgeHandle -- The PCI Root Bridge whose bus range is to be programmed\r
- Configuration -- The pointer to the PCI bus resource descriptor\r
- \r
-Returns:\r
-\r
---*/ \r
{\r
LIST_ENTRY *List; \r
PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
}\r
\r
\r
+/**\r
+ Submits the I/O and memory resource requirements for the specified PCI root\r
+ bridge.\r
+\r
+ This function is used to submit all the I/O and memory resources that are\r
+ required by the specified PCI root bridge. The input parameter Configuration\r
+ is used to specify the following:\r
+ - The various types of resources that are required\r
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+ @param[in] This Pointer to the\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance.\r
+\r
+ @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory\r
+ resource requirements are being submitted.\r
+\r
+ @param[in] Configuration The pointer to the PCI I/O and PCI memory\r
+ resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The I/O and memory resource requests for a PCI\r
+ root bridge were accepted.\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
+ handle.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI\r
+ 2.0 resource descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration includes requests for one or\r
+ more resource types that are not supported by\r
+ this PCI root bridge. This error will happen\r
+ if the caller did not combine resources\r
+ according to Attributes that were returned by\r
+ GetAllocAttributes().\r
+\r
+ @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r
+\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI\r
+ root bridge.\r
+\r
+ @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for\r
+ this PCI root bridge.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
SubmitResources(\r
IN EFI_HANDLE RootBridgeHandle,\r
IN VOID *Configuration\r
)\r
-/*++\r
-\r
-Routine Description:\r
- Submits the I/O and memory resource requirements for the specified PCI Root Bridge\r
- \r
-Arguments:\r
- This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
- RootBridgeHandle -- The PCI Root Bridge whose I/O and memory resource requirements \r
- are being submitted\r
- Configuration -- The pointer to the PCI I/O and PCI memory resource descriptor \r
-Returns:\r
-\r
---*/ \r
{\r
LIST_ENTRY *List; \r
PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
UINT8 *Temp;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
UINT64 AddrLen;\r
UINT64 Alignment;\r
\r
RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
while ( *Temp == 0x8A) {\r
- ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
\r
//\r
// Check Address Length\r
//\r
- if (ptr->AddrLen > 0xffffffff) {\r
+ if (Ptr->AddrLen > 0xffffffff) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
// Check address range alignment\r
//\r
- if (ptr->AddrRangeMax >= 0xffffffff || ptr->AddrRangeMax != (GetPowerOfTwo64 (ptr->AddrRangeMax + 1) - 1)) {\r
+ if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- switch (ptr->ResType) {\r
+ switch (Ptr->ResType) {\r
\r
case 0:\r
\r
//\r
// Check invalid Address Sapce Granularity\r
//\r
- if (ptr->AddrSpaceGranularity != 32) {\r
+ if (Ptr->AddrSpaceGranularity != 32) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
// check the memory resource request is supported by PCI root bridge\r
//\r
if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&\r
- ptr->SpecificFlag == 0x06) {\r
+ Ptr->SpecificFlag == 0x06) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- AddrLen = ptr->AddrLen;\r
- Alignment = ptr->AddrRangeMax;\r
- if (ptr->AddrSpaceGranularity == 32) {\r
- if (ptr->SpecificFlag == 0x06) {\r
+ AddrLen = Ptr->AddrLen;\r
+ Alignment = Ptr->AddrRangeMax;\r
+ if (Ptr->AddrSpaceGranularity == 32) {\r
+ if (Ptr->SpecificFlag == 0x06) {\r
//\r
// Apply from GCD\r
//\r
}\r
}\r
\r
- if (ptr->AddrSpaceGranularity == 64) {\r
- if (ptr->SpecificFlag == 0x06) {\r
+ if (Ptr->AddrSpaceGranularity == 64) {\r
+ if (Ptr->SpecificFlag == 0x06) {\r
RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;\r
} else {\r
RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;\r
break;\r
\r
case 1:\r
- AddrLen = (UINTN)ptr->AddrLen;\r
- Alignment = (UINTN)ptr->AddrRangeMax;\r
+ AddrLen = (UINTN) Ptr->AddrLen;\r
+ Alignment = (UINTN) Ptr->AddrRangeMax;\r
RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;\r
RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r
RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
+/**\r
+ Returns the proposed resource settings for the specified PCI root bridge.\r
+\r
+ This member function returns the proposed resource settings for the\r
+ specified PCI root bridge. The proposed resource settings are prepared when\r
+ NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResources.\r
+ The output parameter Configuration specifies the following:\r
+ - The various types of resources, excluding bus resources, that are\r
+ allocated\r
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+ @param[in] This Pointer to the\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance.\r
+\r
+ @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is\r
+ defined in InstallProtocolInterface() in the\r
+ UEFI 2.0 Specification.\r
+\r
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and\r
+ memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
+ handle.\r
+\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
+ lack of resources.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
GetProposedResources(\r
IN EFI_HANDLE RootBridgeHandle,\r
OUT VOID **Configuration\r
)\r
-/*++\r
-\r
-Routine Description:\r
- This function returns the proposed resource settings for the specified \r
- PCI Root Bridge\r
-\r
-Arguments:\r
- This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
- RootBridgeHandle -- The PCI Root Bridge handle\r
- Configuration -- The pointer to the pointer to the PCI I/O \r
- and memory resource descriptor\r
- \r
-Returns:\r
-\r
---*/ \r
{\r
LIST_ENTRY *List; \r
PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
UINTN Number; \r
VOID *Buffer; \r
UINT8 *Temp;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
UINT64 ResStatus;\r
\r
Buffer = NULL;\r
Temp = Buffer;\r
for (Index = 0; Index < TypeBus; Index ++) {\r
if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
- ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r
\r
switch (Index) {\r
//\r
// Io\r
//\r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 1;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 0;\r
- ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = \\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 1;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 0;\r
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = \\r
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
- ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
break;\r
\r
case TypeMem32:\r
//\r
// Memory 32\r
// \r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 0;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 0;\r
- ptr->AddrSpaceGranularity = 32;\r
- ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = \\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 0;\r
+ Ptr->AddrSpaceGranularity = 32;\r
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = \\r
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; \r
- ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
break;\r
\r
case TypePMem32:\r
//\r
// Prefetch memory 32\r
//\r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 0;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 6;\r
- ptr->AddrSpaceGranularity = 32;\r
- ptr->AddrRangeMin = 0;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
- ptr->AddrLen = 0;\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 6;\r
+ Ptr->AddrSpaceGranularity = 32;\r
+ Ptr->AddrRangeMin = 0;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
+ Ptr->AddrLen = 0;\r
break;\r
\r
case TypeMem64:\r
//\r
// Memory 64\r
//\r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 0;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 0;\r
- ptr->AddrSpaceGranularity = 64;\r
- ptr->AddrRangeMin = 0;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
- ptr->AddrLen = 0;\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 0;\r
+ Ptr->AddrSpaceGranularity = 64;\r
+ Ptr->AddrRangeMin = 0;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
+ Ptr->AddrLen = 0;\r
break;\r
\r
case TypePMem64:\r
//\r
// Prefetch memory 64\r
//\r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 0;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 6;\r
- ptr->AddrSpaceGranularity = 64;\r
- ptr->AddrRangeMin = 0;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
- ptr->AddrLen = 0;\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 6;\r
+ Ptr->AddrSpaceGranularity = 64;\r
+ Ptr->AddrRangeMin = 0;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
+ Ptr->AddrLen = 0;\r
break;\r
};\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
-STATIC\r
-VOID\r
-UpdateRootBridgeAttributes (\r
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress\r
- )\r
-{\r
- EFI_STATUS Status;\r
- PCI_TYPE01 PciConfigurationHeader;\r
- UINT64 Attributes;\r
+/**\r
+ Provides the hooks from the PCI bus driver to every PCI controller\r
+ (device/function) at various stages of the PCI enumeration process that allow\r
+ the host bridge driver to preinitialize individual PCI controllers before\r
+ enumeration.\r
\r
- //\r
- // Read the PCI Configuration Header for the device\r
- //\r
- Status = RootBridge->Io.Pci.Read (\r
- &RootBridge->Io,\r
- EfiPciWidthUint16,\r
- EFI_PCI_ADDRESS(\r
- PciAddress.Bus,\r
- PciAddress.Device,\r
- PciAddress.Function,\r
- 0\r
- ),\r
- sizeof (PciConfigurationHeader) / sizeof (UINT16),\r
- &PciConfigurationHeader\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return;\r
- }\r
+ This function is called during the PCI enumeration process. No specific\r
+ action is expected from this member function. It allows the host bridge\r
+ driver to preinitialize individual PCI controllers before enumeration.\r
\r
- Attributes = RootBridge->Attributes;\r
+ @param This Pointer to the\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance.\r
\r
- //\r
- // Look for devices with the VGA Palette Snoop enabled in the COMMAND register of the PCI Config Header\r
- //\r
- if (PciConfigurationHeader.Hdr.Command & 0x20) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- }\r
+ @param RootBridgeHandle The associated PCI root bridge handle. Type\r
+ EFI_HANDLE is defined in InstallProtocolInterface()\r
+ in the UEFI 2.0 Specification.\r
\r
- //\r
- // If the device is a PCI-PCI Bridge, then look at the Subordinate Bus Number\r
- //\r
- if (IS_PCI_BRIDGE(&PciConfigurationHeader)) {\r
- //\r
- // Look at the PPB Configuration for legacy decoding attributes\r
- //\r
- if (PciConfigurationHeader.Bridge.BridgeControl & 0x04) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
- }\r
- if (PciConfigurationHeader.Bridge.BridgeControl & 0x08) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
- }\r
- } else {\r
- //\r
- // See if the PCI device is an IDE controller\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x01 &&\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ) {\r
- if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x80) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
- }\r
- if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x01) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
- }\r
- if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x04) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
- }\r
- }\r
+ @param PciAddress The address of the PCI device on the PCI bus. This\r
+ address can be passed to the\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to\r
+ access the PCI configuration space of the device.\r
+ See Table 12-1 in the UEFI 2.0 Specification for the\r
+ definition of\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
\r
- //\r
- // See if the PCI device is a legacy VGA controller\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x00 &&\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
- }\r
+ @param Phase The phase of the PCI device enumeration.\r
\r
- //\r
- // See if the PCI device is a standard VGA controller\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x03 &&\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x00 ) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
- }\r
- }\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
\r
- RootBridge->Attributes = Attributes;\r
- RootBridge->Supports = Attributes;\r
-}\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
+ handle.\r
\r
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined\r
+ in\r
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ The PCI enumerator should not enumerate this\r
+ device, including its child devices if it is\r
+ a PCI-to-PCI bridge.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
PreprocessController (\r
- IN struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
IN EFI_HANDLE RootBridgeHandle,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
)\r
-/*++\r
-\r
-Routine Description:\r
- This function is called for all the PCI controllers that the PCI \r
- bus driver finds. Can be used to Preprogram the controller.\r
-\r
-Arguments:\r
- This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
- RootBridgeHandle -- The PCI Root Bridge handle\r
- PciBusAddress -- Address of the controller on the PCI bus\r
- Phase -- The Phase during resource allocation\r
- \r
-Returns:\r
- EFI_SUCCESS\r
---*/ \r
{\r
PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
while (List != &HostBridgeInstance->Head) {\r
RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
- UpdateRootBridgeAttributes (\r
- RootBridgeInstance,\r
- PciAddress\r
- );\r
- return EFI_SUCCESS;\r
+ break;\r
}\r
List = List->ForwardLink;\r
}\r
+ if (List == &HostBridgeInstance->Head) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
\r
- return EFI_INVALID_PARAMETER;\r
+ if ((UINT32)Phase > EfiPciBeforeResourceCollection) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
}\r
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