Remove IO and MMIO GCD add operations from this generic PCI Hot Bridge drivers.

[mirror_edk2.git] / PcAtChipsetPkg / PciHostBridgeDxe / PciHostBridge.c

diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
index c2f04ec8072ea6a4f765ec987b3b9e1222dcedd2..b05b4153492ce2b1be5055a72414bd595bf3d217 100644 (file)
--- a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
+++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
@@ -1,7 +1,7 @@
 /** @file\r
   Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation\r
 \r
-Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved. <BR>\r
+Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials are\r
 licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -14,17 +14,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #include "PciHostBridge.h"\r
 \r
-//\r
-// Support 64 K IO space\r
-//\r
-#define RES_IO_BASE   0x1000\r
-#define RES_IO_LIMIT  0xFFFF\r
-//\r
-// Support 4G address space\r
-//\r
-#define RES_MEM_BASE_1 0xF8000000\r
-#define RES_MEM_LIMIT_1 (0xFEC00000 - 1)\r
-\r
 //\r
 // Hard code: Root Bridge Number within the host bridge\r
 //            Root Bridge's attribute\r
@@ -51,7 +40,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
 };\r
 \r
 PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[1][1] = {\r
-  {0, 0, 0, 0xffffffff, 0, 1 << 16}\r
+  {0, 0xff, 0x80000000, 0xffffffff, 0, 0xffff}\r
 };\r
 \r
 EFI_HANDLE mDriverImageHandle;\r
@@ -100,8 +89,6 @@ InitializePciHostBridge (
   UINTN                       Loop2;\r
   PCI_HOST_BRIDGE_INSTANCE    *HostBridge;\r
   PCI_ROOT_BRIDGE_INSTANCE    *PrivateData;\r
-  IN EFI_PHYSICAL_ADDRESS     BaseAddress;\r
-  IN UINT64                   Length;\r
  \r
   mDriverImageHandle = ImageHandle;\r
   \r
@@ -162,29 +149,6 @@ InitializePciHostBridge (
     }\r
   } \r
 \r
-  Status = gDS->AddIoSpace (\r
-                  EfiGcdIoTypeIo, \r
-                  RES_IO_BASE, \r
-                  RES_IO_LIMIT - RES_IO_BASE + 1\r
-                  );\r
-  \r
-  // PCI memory space from 3.75Gbytes->(4GBytes - BIOSFWH local APIC etc)\r
-  Status = gDS->AddMemorySpace (\r
-                  EfiGcdMemoryTypeMemoryMappedIo, \r
-                  RES_MEM_BASE_1, \r
-                  (RES_MEM_LIMIT_1 - RES_MEM_BASE_1 + 1),\r
-                  0\r
-                  );\r
-  \r
-  BaseAddress = 0x80000000;\r
-  Length      = RES_MEM_BASE_1 - BaseAddress;\r
-  Status = gDS->AddMemorySpace (\r
-                  EfiGcdMemoryTypeMemoryMappedIo, \r
-                  BaseAddress, \r
-                  Length,\r
-                  0\r
-                  );\r
-  \r
   return EFI_SUCCESS;\r
 }\r
 \r