\r
#include "PciHostBridge.h"\r
\r
-//\r
-// Support 64 K IO space\r
-//\r
-#define RES_IO_BASE 0x1000\r
-#define RES_IO_LIMIT 0xFFFF\r
-//\r
-// Support 4G address space\r
-//\r
-#define RES_MEM_BASE_1 0xF8000000\r
-#define RES_MEM_LIMIT_1 (0xFEC00000 - 1)\r
-\r
//\r
// Hard code: Root Bridge Number within the host bridge\r
// Root Bridge's attribute\r
UINTN Loop2;\r
PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress;\r
- IN UINT64 Length;\r
\r
mDriverImageHandle = ImageHandle;\r
\r
}\r
} \r
\r
- Status = gDS->AddIoSpace (\r
- EfiGcdIoTypeIo, \r
- RES_IO_BASE, \r
- RES_IO_LIMIT - RES_IO_BASE + 1\r
- );\r
- \r
- // PCI memory space from 3.75Gbytes->(4GBytes - BIOSFWH local APIC etc)\r
- Status = gDS->AddMemorySpace (\r
- EfiGcdMemoryTypeMemoryMappedIo, \r
- RES_MEM_BASE_1, \r
- (RES_MEM_LIMIT_1 - RES_MEM_BASE_1 + 1),\r
- 0\r
- );\r
- \r
- BaseAddress = 0x80000000;\r
- Length = RES_MEM_BASE_1 - BaseAddress;\r
- Status = gDS->AddMemorySpace (\r
- EfiGcdMemoryTypeMemoryMappedIo, \r
- BaseAddress, \r
- Length,\r
- 0\r
- );\r
- \r
return EFI_SUCCESS;\r
}\r
\r