-/** @file\r
- PCI Root Bridge Io Protocol implementation\r
-\r
- Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials are licensed and made available\r
- under the terms and conditions of the BSD License which accompanies this\r
- distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-**/\r
-\r
-#include "PciHostBridge.h"\r
-#include "IoFifo.h"\r
-\r
-typedef struct {\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];\r
- EFI_ACPI_END_TAG_DESCRIPTOR EndDesp;\r
-} RESOURCE_CONFIGURATION;\r
-\r
-RESOURCE_CONFIGURATION Configuration = {\r
- {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},\r
- {0x79, 0}\r
-};\r
-\r
-//\r
-// Protocol Member Function Prototypes\r
-//\r
-\r
-/**\r
- Polls an address in memory mapped I/O space until an exit condition is met,\r
- or a timeout occurs.\r
-\r
- This function provides a standard way to poll a PCI memory location. A PCI\r
- memory read operation is performed at the PCI memory address specified by\r
- Address for the width specified by Width. The result of this PCI memory read\r
- operation is stored in Result. This PCI memory read operation is repeated\r
- until either a timeout of Delay 100 ns units has expired, or (Result & Mask)\r
- is equal to Value.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] Address The base address of the memory operations. The caller\r
- is responsible for aligning Address if required.\r
-\r
- @param[in] Mask Mask used for the polling criteria. Bytes above Width\r
- in Mask are ignored. The bits in the bytes below Width\r
- which are zero in Mask are ignored when polling the\r
- memory address.\r
-\r
- @param[in] Value The comparison value used for the polling exit\r
- criteria.\r
-\r
- @param[in] Delay The number of 100 ns units to poll. Note that timer\r
- available may be of poorer granularity.\r
-\r
- @param[out] Result Pointer to the last value read from the memory\r
- location.\r
-\r
- @retval EFI_SUCCESS The last data returned from the access matched\r
- the poll exit criteria.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid.\r
-\r
- @retval EFI_INVALID_PARAMETER Result is NULL.\r
-\r
- @retval EFI_TIMEOUT Delay expired before a match occurred.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPollMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- );\r
-\r
-/**\r
- Reads from the I/O space of a PCI Root Bridge. Returns when either the\r
- polling exit criteria is satisfied or after a defined duration.\r
-\r
- This function provides a standard way to poll a PCI I/O location. A PCI I/O\r
- read operation is performed at the PCI I/O address specified by Address for\r
- the width specified by Width. The result of this PCI I/O read operation is\r
- stored in Result. This PCI I/O read operation is repeated until either a\r
- timeout of Delay 100 ns units has expired, or (Result & Mask) is equal to\r
- Value.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the I/O operations.\r
-\r
- @param[in] Address The base address of the I/O operations. The caller is\r
- responsible for aligning Address if required.\r
-\r
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in\r
- Mask are ignored. The bits in the bytes below Width\r
- which are zero in Mask are ignored when polling the I/O\r
- address.\r
-\r
- @param[in] Value The comparison value used for the polling exit criteria.\r
-\r
-\r
- @param[in] Delay The number of 100 ns units to poll. Note that timer\r
- available may be of poorer granularity.\r
-\r
- @param[out] Result Pointer to the last value read from the memory location.\r
-\r
- @retval EFI_SUCCESS The last data returned from the access matched\r
- the poll exit criteria.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid.\r
-\r
- @retval EFI_INVALID_PARAMETER Result is NULL.\r
-\r
- @retval EFI_TIMEOUT Delay expired before a match occurred.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPollIo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root\r
- bridge memory space.\r
-\r
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r
- controller registers in the PCI root bridge memory space.\r
- The memory operations are carried out exactly as requested. The caller is\r
- responsible for satisfying any alignment and memory width restrictions that a\r
- PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operation.\r
-\r
- @param[in] Address The base address of the memory operation. The caller\r
- is responsible for aligning the Address if required.\r
-\r
- @param[in] Count The number of memory operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
-\r
- @param[out] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMemRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root\r
- bridge memory space.\r
-\r
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r
- controller registers in the PCI root bridge memory space.\r
- The memory operations are carried out exactly as requested. The caller is\r
- responsible for satisfying any alignment and memory width restrictions that a\r
- PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operation.\r
-\r
- @param[in] Address The base address of the memory operation. The caller\r
- is responsible for aligning the Address if required.\r
-\r
- @param[in] Count The number of memory operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
-\r
- @param[in] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMemWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root\r
- bridge I/O space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] UserAddress The base address of the I/O operation. The caller is\r
- responsible for aligning the Address if required.\r
-\r
- @param[in] Count The number of I/O operations to perform. Bytes moved\r
- is Width size * Count, starting at Address.\r
-\r
- @param[out] UserBuffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoIoRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 UserAddress,\r
- IN UINTN Count,\r
- OUT VOID *UserBuffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root\r
- bridge I/O space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] UserAddress The base address of the I/O operation. The caller is\r
- responsible for aligning the Address if required.\r
-\r
- @param[in] Count The number of I/O operations to perform. Bytes moved\r
- is Width size * Count, starting at Address.\r
-\r
- @param[in] UserBuffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoIoWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 UserAddress,\r
- IN UINTN Count,\r
- IN VOID *UserBuffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to copy one region of PCI root bridge memory space to\r
- another region of PCI root bridge memory space.\r
-\r
- The CopyMem() function enables a PCI driver to copy one region of PCI root\r
- bridge memory space to another region of PCI root bridge memory space. This\r
- is especially useful for video scroll operation on a memory mapped video\r
- buffer.\r
- The memory operations are carried out exactly as requested. The caller is\r
- responsible for satisfying any alignment and memory width restrictions that a\r
- PCI root bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
- instance.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] DestAddress The destination address of the memory operation. The\r
- caller is responsible for aligning the DestAddress if\r
- required.\r
-\r
- @param[in] SrcAddress The source address of the memory operation. The caller\r
- is responsible for aligning the SrcAddress if\r
- required.\r
-\r
- @param[in] Count The number of memory operations to perform. Bytes\r
- moved is Width size * Count, starting at DestAddress\r
- and SrcAddress.\r
-\r
-\r
- @retval EFI_SUCCESS The data was copied from one memory region\r
- to another memory region.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoCopyMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 DestAddress,\r
- IN UINT64 SrcAddress,\r
- IN UINTN Count\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in a PCI root\r
- bridge's configuration space.\r
-\r
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI\r
- configuration registers for a PCI controller.\r
- The PCI Configuration operations are carried out exactly as requested. The\r
- caller is responsible for any alignment and PCI configuration width issues\r
- that a PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] Address The address within the PCI configuration space for the\r
- PCI controller.\r
-\r
- @param[in] Count The number of PCI configuration operations to perform.\r
- Bytes moved is Width size * Count, starting at\r
- Address.\r
-\r
- @param[out] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPciRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in a PCI root\r
- bridge's configuration space.\r
-\r
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI\r
- configuration registers for a PCI controller.\r
- The PCI Configuration operations are carried out exactly as requested. The\r
- caller is responsible for any alignment and PCI configuration width issues\r
- that a PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] Address The address within the PCI configuration space for the\r
- PCI controller.\r
-\r
- @param[in] Count The number of PCI configuration operations to perform.\r
- Bytes moved is Width size * Count, starting at\r
- Address.\r
-\r
- @param[in] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPciWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
-\r
-/**\r
- Provides the PCI controller-specific addresses required to access system\r
- memory from a DMA bus master.\r
-\r
- The Map() function provides the PCI controller specific addresses needed to\r
- access system memory. This function is used to map system memory for PCI bus\r
- master DMA accesses.\r
-\r
- @param[in] This A pointer to the\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Operation Indicates if the bus master is going to read\r
- or write to system memory.\r
-\r
- @param[in] HostAddress The system memory address to map to the PCI\r
- controller.\r
-\r
- @param[in, out] NumberOfBytes On input the number of bytes to map. On\r
- output the number of bytes that were mapped.\r
-\r
- @param[out] DeviceAddress The resulting map address for the bus master\r
- PCI controller to use to access the system\r
- memory's HostAddress.\r
-\r
- @param[out] Mapping The value to pass to Unmap() when the bus\r
- master DMA operation is complete.\r
-\r
- @retval EFI_SUCCESS The range was mapped for the returned\r
- NumberOfBytes.\r
-\r
- @retval EFI_INVALID_PARAMETER Operation is invalid.\r
-\r
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
-\r
- @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.\r
-\r
- @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.\r
-\r
- @retval EFI_INVALID_PARAMETER Mapping is NULL.\r
-\r
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common\r
- buffer.\r
-\r
- @retval EFI_DEVICE_ERROR The system hardware could not map the\r
- requested address.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
- IN VOID *HostAddress,\r
- IN OUT UINTN *NumberOfBytes,\r
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
- OUT VOID **Mapping\r
- );\r
-\r
-/**\r
- Completes the Map() operation and releases any corresponding resources.\r
-\r
- The Unmap() function completes the Map() operation and releases any\r
- corresponding resources.\r
- If the operation was an EfiPciOperationBusMasterWrite or\r
- EfiPciOperationBusMasterWrite64, the data is committed to the target system\r
- memory.\r
- Any resources used for the mapping are freed.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Mapping The mapping value returned from Map().\r
-\r
- @retval EFI_SUCCESS The range was unmapped.\r
-\r
- @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by\r
- Map().\r
-\r
- @retval EFI_DEVICE_ERROR The data was not committed to the target\r
- system memory.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoUnmap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN VOID *Mapping\r
- );\r
-\r
-/**\r
- Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer\r
- or EfiPciOperationBusMasterCommonBuffer64 mapping.\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param Type This parameter is not used and must be ignored.\r
-\r
- @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
- EfiRuntimeServicesData.\r
-\r
- @param Pages The number of pages to allocate.\r
-\r
- @param HostAddress A pointer to store the base system memory address of the\r
- allocated range.\r
-\r
- @param Attributes The requested bit mask of attributes for the allocated\r
- range. Only the attributes\r
- EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,\r
- EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and\r
- EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this\r
- function.\r
-\r
- @retval EFI_SUCCESS The requested memory pages were allocated.\r
-\r
- @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r
-\r
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
-\r
- @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal\r
- attribute bits are MEMORY_WRITE_COMBINE,\r
- MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoAllocateBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_ALLOCATE_TYPE Type,\r
- IN EFI_MEMORY_TYPE MemoryType,\r
- IN UINTN Pages,\r
- OUT VOID **HostAddress,\r
- IN UINT64 Attributes\r
- );\r
-\r
-/**\r
- Frees memory that was allocated with AllocateBuffer().\r
-\r
- The FreeBuffer() function frees memory that was allocated with\r
- AllocateBuffer().\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param Pages The number of pages to free.\r
-\r
- @param HostAddress The base system memory address of the allocated range.\r
-\r
- @retval EFI_SUCCESS The requested memory pages were freed.\r
-\r
- @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and\r
- Pages was not allocated with AllocateBuffer().\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoFreeBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINTN Pages,\r
- OUT VOID *HostAddress\r
- );\r
-\r
-/**\r
- Flushes all PCI posted write transactions from a PCI host bridge to system\r
- memory.\r
-\r
- The Flush() function flushes any PCI posted write transactions from a PCI\r
- host bridge to system memory. Posted write transactions are generated by PCI\r
- bus masters when they perform write transactions to target addresses in\r
- system memory.\r
- This function does not flush posted write transactions from any PCI bridges.\r
- A PCI controller specific action must be taken to guarantee that the posted\r
- write transactions have been flushed from the PCI controller and from all the\r
- PCI bridges into the PCI host bridge. This is typically done with a PCI read\r
- transaction from the PCI controller prior to calling Flush().\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @retval EFI_SUCCESS The PCI posted write transactions were flushed\r
- from the PCI host bridge to system memory.\r
-\r
- @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed\r
- from the PCI host bridge due to a hardware error.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoFlush (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
- );\r
-\r
-/**\r
- Gets the attributes that a PCI root bridge supports setting with\r
- SetAttributes(), and the attributes that a PCI root bridge is currently\r
- using.\r
-\r
- The GetAttributes() function returns the mask of attributes that this PCI\r
- root bridge supports and the mask of attributes that the PCI root bridge is\r
- currently using.\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param Supported A pointer to the mask of attributes that this PCI root\r
- bridge supports setting with SetAttributes().\r
-\r
- @param Attributes A pointer to the mask of attributes that this PCI root\r
- bridge is currently using.\r
-\r
-\r
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes\r
- that the PCI root bridge supports is returned\r
- in Supports. If Attributes is not NULL, then\r
- the attributes that the PCI root bridge is\r
- currently using is returned in Attributes.\r
-\r
- @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoGetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT UINT64 *Supported,\r
- OUT UINT64 *Attributes\r
- );\r
-\r
-/**\r
- Sets attributes for a resource range on a PCI root bridge.\r
-\r
- The SetAttributes() function sets the attributes specified in Attributes for\r
- the PCI root bridge on the resource range specified by ResourceBase and\r
- ResourceLength. Since the granularity of setting these attributes may vary\r
- from resource type to resource type, and from platform to platform, the\r
- actual resource range and the one passed in by the caller may differ. As a\r
- result, this function may set the attributes specified by Attributes on a\r
- larger resource range than the caller requested. The actual range is returned\r
- in ResourceBase and ResourceLength. The caller is responsible for verifying\r
- that the actual range for which the attributes were set is acceptable.\r
-\r
- @param[in] This A pointer to the\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Attributes The mask of attributes to set. If the\r
- attribute bit MEMORY_WRITE_COMBINE,\r
- MEMORY_CACHED, or MEMORY_DISABLE is set,\r
- then the resource range is specified by\r
- ResourceBase and ResourceLength. If\r
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
- MEMORY_DISABLE are not set, then\r
- ResourceBase and ResourceLength are ignored,\r
- and may be NULL.\r
-\r
- @param[in, out] ResourceBase A pointer to the base address of the\r
- resource range to be modified by the\r
- attributes specified by Attributes.\r
-\r
- @param[in, out] ResourceLength A pointer to the length of the resource\r
- range to be modified by the attributes\r
- specified by Attributes.\r
-\r
- @retval EFI_SUCCESS The current configuration of this PCI root bridge\r
- was returned in Resources.\r
-\r
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge\r
- could not be retrieved.\r
-\r
- @retval EFI_INVALID_PARAMETER Invalid pointer of\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoSetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINT64 Attributes,\r
- IN OUT UINT64 *ResourceBase,\r
- IN OUT UINT64 *ResourceLength\r
- );\r
-\r
-/**\r
- Retrieves the current resource settings of this PCI root bridge in the form\r
- of a set of ACPI 2.0 resource descriptors.\r
-\r
- There are only two resource descriptor types from the ACPI Specification that\r
- may be used to describe the current resources allocated to a PCI root bridge.\r
- These are the QWORD Address Space Descriptor (ACPI 2.0 Section 6.4.3.5.1),\r
- and the End Tag (ACPI 2.0 Section 6.4.2.8). The QWORD Address Space\r
- Descriptor can describe memory, I/O, and bus number ranges for dynamic or\r
- fixed resources. The configuration of a PCI root bridge is described with one\r
- or more QWORD Address Space Descriptors followed by an End Tag.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that\r
- describe the current configuration of this PCI root\r
- bridge. The storage for the ACPI 2.0 resource\r
- descriptors is allocated by this function. The\r
- caller must treat the return buffer as read-only\r
- data, and the buffer must not be freed by the\r
- caller.\r
-\r
- @retval EFI_SUCCESS The current configuration of this PCI root bridge\r
- was returned in Resources.\r
-\r
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge\r
- could not be retrieved.\r
-\r
- @retval EFI_INVALID_PARAMETER Invalid pointer of\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoConfiguration (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT VOID **Resources\r
- );\r
-\r
-//\r
-// Memory Controller Pci Root Bridge Io Module Variables\r
-//\r
-EFI_METRONOME_ARCH_PROTOCOL *mMetronome;\r
-\r
-//\r
-// Lookup table for increment values based on transfer widths\r
-//\r
-UINT8 mInStride[] = {\r
- 1, // EfiPciWidthUint8\r
- 2, // EfiPciWidthUint16\r
- 4, // EfiPciWidthUint32\r
- 8, // EfiPciWidthUint64\r
- 0, // EfiPciWidthFifoUint8\r
- 0, // EfiPciWidthFifoUint16\r
- 0, // EfiPciWidthFifoUint32\r
- 0, // EfiPciWidthFifoUint64\r
- 1, // EfiPciWidthFillUint8\r
- 2, // EfiPciWidthFillUint16\r
- 4, // EfiPciWidthFillUint32\r
- 8 // EfiPciWidthFillUint64\r
-};\r
-\r
-//\r
-// Lookup table for increment values based on transfer widths\r
-//\r
-UINT8 mOutStride[] = {\r
- 1, // EfiPciWidthUint8\r
- 2, // EfiPciWidthUint16\r
- 4, // EfiPciWidthUint32\r
- 8, // EfiPciWidthUint64\r
- 1, // EfiPciWidthFifoUint8\r
- 2, // EfiPciWidthFifoUint16\r
- 4, // EfiPciWidthFifoUint32\r
- 8, // EfiPciWidthFifoUint64\r
- 0, // EfiPciWidthFillUint8\r
- 0, // EfiPciWidthFillUint16\r
- 0, // EfiPciWidthFillUint32\r
- 0 // EfiPciWidthFillUint64\r
-};\r
-\r
-/**\r
- Construct the Pci Root Bridge Io protocol\r
-\r
- @param Protocol Point to protocol instance\r
-\r
- @param HostBridgeHandle Handle of host bridge\r
-\r
- @param Attri Attribute of host bridge\r
-\r
- @param ResAperture ResourceAperture for host bridge\r
-\r
- @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
-**/\r
-EFI_STATUS\r
-RootBridgeConstructor (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
- IN EFI_HANDLE HostBridgeHandle,\r
- IN UINT64 Attri,\r
- IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r
- )\r
-{\r
- EFI_STATUS Status;\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- PCI_RESOURCE_TYPE Index;\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);\r
-\r
- //\r
- // The host to pci bridge, the host memory and io addresses are\r
- // direct mapped to pci addresses, so no need translate, set bases to 0.\r
- //\r
- PrivateData->MemBase = ResAperture->MemBase;\r
- PrivateData->IoBase = ResAperture->IoBase;\r
-\r
- //\r
- // The host bridge only supports 32bit addressing for memory\r
- // and standard IA32 16bit io\r
- //\r
- PrivateData->MemLimit = ResAperture->MemLimit;\r
- PrivateData->IoLimit = ResAperture->IoLimit;\r
-\r
- //\r
- // Bus Aperture for this Root Bridge (Possible Range)\r
- //\r
- PrivateData->BusBase = ResAperture->BusBase;\r
- PrivateData->BusLimit = ResAperture->BusLimit;\r
-\r
- //\r
- // Specific for this chipset\r
- //\r
- for (Index = TypeIo; Index < TypeMax; Index++) {\r
- PrivateData->ResAllocNode[Index].Type = Index;\r
- PrivateData->ResAllocNode[Index].Base = 0;\r
- PrivateData->ResAllocNode[Index].Length = 0;\r
- PrivateData->ResAllocNode[Index].Status = ResNone;\r
- }\r
-\r
- PrivateData->RootBridgeAttrib = Attri;\r
-\r
- PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
- EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
- EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
- EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
- EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
- EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
- EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
- PrivateData->Attributes = PrivateData->Supports;\r
-\r
- Protocol->ParentHandle = HostBridgeHandle;\r
-\r
- Protocol->PollMem = RootBridgeIoPollMem;\r
- Protocol->PollIo = RootBridgeIoPollIo;\r
-\r
- Protocol->Mem.Read = RootBridgeIoMemRead;\r
- Protocol->Mem.Write = RootBridgeIoMemWrite;\r
-\r
- Protocol->Io.Read = RootBridgeIoIoRead;\r
- Protocol->Io.Write = RootBridgeIoIoWrite;\r
-\r
- Protocol->CopyMem = RootBridgeIoCopyMem;\r
-\r
- Protocol->Pci.Read = RootBridgeIoPciRead;\r
- Protocol->Pci.Write = RootBridgeIoPciWrite;\r
-\r
- Protocol->Map = RootBridgeIoMap;\r
- Protocol->Unmap = RootBridgeIoUnmap;\r
-\r
- Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;\r
- Protocol->FreeBuffer = RootBridgeIoFreeBuffer;\r
-\r
- Protocol->Flush = RootBridgeIoFlush;\r
-\r
- Protocol->GetAttributes = RootBridgeIoGetAttributes;\r
- Protocol->SetAttributes = RootBridgeIoSetAttributes;\r
-\r
- Protocol->Configuration = RootBridgeIoConfiguration;\r
-\r
- Protocol->SegmentNumber = 0;\r
-\r
- Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL,\r
- (VOID **)&mMetronome);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.\r
-\r
- The I/O operations are carried out exactly as requested. The caller is\r
- responsible for satisfying any alignment and I/O width restrictions that a PI\r
- System on a platform might require. For example on some platforms, width\r
- requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other\r
- hand, will be handled by the driver.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] OperationType I/O operation type: IO/MMIO/PCI.\r
-\r
- @param[in] Width Signifies the width of the I/O or Memory operation.\r
-\r
- @param[in] Address The base address of the I/O operation.\r
-\r
- @param[in] Count The number of I/O operations to perform. The number\r
- of bytes moved is Width size * Count, starting at\r
- Address.\r
-\r
- @param[in] Buffer For read operations, the destination buffer to\r
- store the results. For write operations, the source\r
- buffer from which to write data.\r
-\r
- @retval EFI_SUCCESS The parameters for this request pass the\r
- checks.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
-\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
- and Count is not valid for this PI system.\r
-**/\r
-EFI_STATUS\r
-RootBridgeIoCheckParameter (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN OPERATION_TYPE OperationType,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r
- UINT64 MaxCount;\r
- UINT64 Base;\r
- UINT64 Limit;\r
-\r
- //\r
- // Check to see if Buffer is NULL\r
- //\r
- if (Buffer == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Check to see if Width is in the valid range\r
- //\r
- if ((UINT32)Width >= EfiPciWidthMaximum) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // For FIFO type, the target address won't increase during the access,\r
- // so treat Count as 1\r
- //\r
- if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
- Count = 1;\r
- }\r
-\r
- //\r
- // Check to see if Width is in the valid range for I/O Port operations\r
- //\r
- Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {\r
- ASSERT (FALSE);\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Check to see if Address is aligned\r
- //\r
- if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
-\r
- //\r
- // Check to see if any address associated with this transfer exceeds the\r
- // maximum allowed address. The maximum address implied by the parameters\r
- // passed in is Address + Size * Count. If the following condition is met,\r
- // then the transfer is not supported.\r
- //\r
- // Address + Size * Count > Limit + 1\r
- //\r
- // Since Limit can be the maximum integer value supported by the CPU and\r
- // Count can also be the maximum integer value supported by the CPU, this\r
- // range check must be adjusted to avoid all oveflow conditions.\r
- //\r
- // The following form of the range check is equivalent but assumes that\r
- // Limit is of the form (2^n - 1).\r
- //\r
- if (OperationType == IoOperation) {\r
- Base = PrivateData->IoBase;\r
- Limit = PrivateData->IoLimit;\r
- } else if (OperationType == MemOperation) {\r
- Base = PrivateData->MemBase;\r
- Limit = PrivateData->MemLimit;\r
- } else {\r
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
- if (PciRbAddr->Bus < PrivateData->BusBase ||\r
- PciRbAddr->Bus > PrivateData->BusLimit) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER ||\r
- PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if (PciRbAddr->ExtendedRegister != 0) {\r
- Address = PciRbAddr->ExtendedRegister;\r
- } else {\r
- Address = PciRbAddr->Register;\r
- }\r
- Base = 0;\r
- Limit = MAX_PCI_REG_ADDRESS;\r
- }\r
-\r
- if (Address < Base) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if (Count == 0) {\r
- if (Address > Limit) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- } else {\r
- MaxCount = RShiftU64 (Limit, Width);\r
- if (MaxCount < (Count - 1)) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Internal help function for read and write memory space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Write Switch value for Read or Write.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] UserAddress The address within the PCI configuration space for\r
- the PCI controller.\r
-\r
- @param[in] Count The number of PCI configuration operations to\r
- perform. Bytes moved is Width size * Count,\r
- starting at Address.\r
-\r
- @param[in, out] UserBuffer For read operations, the destination buffer to\r
- store the results. For write operations, the\r
- source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-RootBridgeIoMemRW (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN BOOLEAN Write,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
-\r
- Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,\r
- Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- for (Uint8Buffer = Buffer;\r
- Count > 0;\r
- Address += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (Write) {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
- break;\r
- case EfiPciWidthUint16:\r
- MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
- break;\r
- case EfiPciWidthUint32:\r
- MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
- break;\r
- case EfiPciWidthUint64:\r
- MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- } else {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint16:\r
- *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint32:\r
- *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint64:\r
- *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- }\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Internal help function for read and write IO space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Write Switch value for Read or Write.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] UserAddress The address within the PCI configuration space for\r
- the PCI controller.\r
-\r
- @param[in] Count The number of PCI configuration operations to\r
- perform. Bytes moved is Width size * Count,\r
- starting at Address.\r
-\r
- @param[in, out] UserBuffer For read operations, the destination buffer to\r
- store the results. For write operations, the\r
- source buffer to write data from.\r
-\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-RootBridgeIoIoRW (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN BOOLEAN Write,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
-\r
- Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address,\r
- Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
-\r
-#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
- if (InStride == 0) {\r
- if (Write) {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- IoWriteFifo8 ((UINTN) Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiPciWidthUint16:\r
- IoWriteFifo16 ((UINTN) Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiPciWidthUint32:\r
- IoWriteFifo32 ((UINTN) Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- } else {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- IoReadFifo8 ((UINTN) Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiPciWidthUint16:\r
- IoReadFifo16 ((UINTN) Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiPciWidthUint32:\r
- IoReadFifo32 ((UINTN) Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- }\r
- }\r
-#endif\r
-\r
- for (Uint8Buffer = Buffer;\r
- Count > 0;\r
- Address += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (Write) {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- IoWrite8 ((UINTN)Address, *Uint8Buffer);\r
- break;\r
- case EfiPciWidthUint16:\r
- IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
- break;\r
- case EfiPciWidthUint32:\r
- IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- } else {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- *Uint8Buffer = IoRead8 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint16:\r
- *((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint32:\r
- *((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- }\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Internal help function for read and write PCI configuration space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Write Switch value for Read or Write.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] UserAddress The address within the PCI configuration space for\r
- the PCI controller.\r
-\r
- @param[in] Count The number of PCI configuration operations to\r
- perform. Bytes moved is Width size * Count,\r
- starting at Address.\r
-\r
- @param[in, out] UserBuffer For read operations, the destination buffer to\r
- store the results. For write operations, the\r
- source buffer to write data from.\r
-\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-RootBridgeIoPciRW (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN BOOLEAN Write,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r
- UINTN PcieRegAddr;\r
-\r
- Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address,\r
- Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
-\r
- PcieRegAddr = (UINTN) PCI_LIB_ADDRESS (\r
- PciRbAddr->Bus,\r
- PciRbAddr->Device,\r
- PciRbAddr->Function,\r
- (PciRbAddr->ExtendedRegister != 0) ? \\r
- PciRbAddr->ExtendedRegister :\r
- PciRbAddr->Register\r
- );\r
-\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- for (Uint8Buffer = Buffer;\r
- Count > 0;\r
- PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (Write) {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- PciWrite8 (PcieRegAddr, *Uint8Buffer);\r
- break;\r
- case EfiPciWidthUint16:\r
- PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer));\r
- break;\r
- case EfiPciWidthUint32:\r
- PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- } else {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- *Uint8Buffer = PciRead8 (PcieRegAddr);\r
- break;\r
- case EfiPciWidthUint16:\r
- *((UINT16 *)Uint8Buffer) = PciRead16 (PcieRegAddr);\r
- break;\r
- case EfiPciWidthUint32:\r
- *((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Polls an address in memory mapped I/O space until an exit condition is met,\r
- or a timeout occurs.\r
-\r
- This function provides a standard way to poll a PCI memory location. A PCI\r
- memory read operation is performed at the PCI memory address specified by\r
- Address for the width specified by Width. The result of this PCI memory read\r
- operation is stored in Result. This PCI memory read operation is repeated\r
- until either a timeout of Delay 100 ns units has expired, or (Result & Mask)\r
- is equal to Value.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] Address The base address of the memory operations. The caller\r
- is responsible for aligning Address if required.\r
-\r
- @param[in] Mask Mask used for the polling criteria. Bytes above Width\r
- in Mask are ignored. The bits in the bytes below Width\r
- which are zero in Mask are ignored when polling the\r
- memory address.\r
-\r
- @param[in] Value The comparison value used for the polling exit\r
- criteria.\r
-\r
- @param[in] Delay The number of 100 ns units to poll. Note that timer\r
- available may be of poorer granularity.\r
-\r
- @param[out] Result Pointer to the last value read from the memory\r
- location.\r
-\r
- @retval EFI_SUCCESS The last data returned from the access matched\r
- the poll exit criteria.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid.\r
-\r
- @retval EFI_INVALID_PARAMETER Result is NULL.\r
-\r
- @retval EFI_TIMEOUT Delay expired before a match occurred.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPollMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT64 NumberOfTicks;\r
- UINT32 Remainder;\r
-\r
- if (Result == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((UINT32)Width > EfiPciWidthUint64) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // No matter what, always do a single poll.\r
- //\r
- Status = This->Mem.Read (This, Width, Address, 1, Result);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- if ((*Result & Mask) == Value) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- if (Delay == 0) {\r
- return EFI_SUCCESS;\r
-\r
- } else {\r
-\r
- //\r
- // Determine the proper # of metronome ticks to wait for polling the\r
- // location. The nuber of ticks is Roundup (Delay /\r
- // mMetronome->TickPeriod)+1\r
- // The "+1" to account for the possibility of the first tick being short\r
- // because we started in the middle of a tick.\r
- //\r
- // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome\r
- // protocol definition is updated.\r
- //\r
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod,\r
- &Remainder);\r
- if (Remainder != 0) {\r
- NumberOfTicks += 1;\r
- }\r
- NumberOfTicks += 1;\r
-\r
- while (NumberOfTicks != 0) {\r
-\r
- mMetronome->WaitForTick (mMetronome, 1);\r
-\r
- Status = This->Mem.Read (This, Width, Address, 1, Result);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- if ((*Result & Mask) == Value) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- NumberOfTicks -= 1;\r
- }\r
- }\r
- return EFI_TIMEOUT;\r
-}\r
-\r
-/**\r
- Reads from the I/O space of a PCI Root Bridge. Returns when either the\r
- polling exit criteria is satisfied or after a defined duration.\r
-\r
- This function provides a standard way to poll a PCI I/O location. A PCI I/O\r
- read operation is performed at the PCI I/O address specified by Address for\r
- the width specified by Width.\r
- The result of this PCI I/O read operation is stored in Result. This PCI I/O\r
- read operation is repeated until either a timeout of Delay 100 ns units has\r
- expired, or (Result & Mask) is equal to Value.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the I/O operations.\r
-\r
- @param[in] Address The base address of the I/O operations. The caller is\r
- responsible for aligning Address if required.\r
-\r
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in\r
- Mask are ignored. The bits in the bytes below Width\r
- which are zero in Mask are ignored when polling the I/O\r
- address.\r
-\r
- @param[in] Value The comparison value used for the polling exit criteria.\r
-\r
- @param[in] Delay The number of 100 ns units to poll. Note that timer\r
- available may be of poorer granularity.\r
-\r
- @param[out] Result Pointer to the last value read from the memory location.\r
-\r
- @retval EFI_SUCCESS The last data returned from the access matched\r
- the poll exit criteria.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid.\r
-\r
- @retval EFI_INVALID_PARAMETER Result is NULL.\r
-\r
- @retval EFI_TIMEOUT Delay expired before a match occurred.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPollIo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT64 NumberOfTicks;\r
- UINT32 Remainder;\r
-\r
- //\r
- // No matter what, always do a single poll.\r
- //\r
-\r
- if (Result == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((UINT32)Width > EfiPciWidthUint64) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- Status = This->Io.Read (This, Width, Address, 1, Result);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- if ((*Result & Mask) == Value) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- if (Delay == 0) {\r
- return EFI_SUCCESS;\r
-\r
- } else {\r
-\r
- //\r
- // Determine the proper # of metronome ticks to wait for polling the\r
- // location. The number of ticks is Roundup (Delay /\r
- // mMetronome->TickPeriod)+1\r
- // The "+1" to account for the possibility of the first tick being short\r
- // because we started in the middle of a tick.\r
- //\r
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod,\r
- &Remainder);\r
- if (Remainder != 0) {\r
- NumberOfTicks += 1;\r
- }\r
- NumberOfTicks += 1;\r
-\r
- while (NumberOfTicks != 0) {\r
-\r
- mMetronome->WaitForTick (mMetronome, 1);\r
-\r
- Status = This->Io.Read (This, Width, Address, 1, Result);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- if ((*Result & Mask) == Value) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- NumberOfTicks -= 1;\r
- }\r
- }\r
- return EFI_TIMEOUT;\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root\r
- bridge memory space.\r
-\r
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r
- controller registers in the PCI root bridge memory space.\r
- The memory operations are carried out exactly as requested. The caller is\r
- responsible for satisfying any alignment and memory width restrictions that a\r
- PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operation.\r
-\r
- @param[in] Address The base address of the memory operation. The caller\r
- is responsible for aligning the Address if required.\r
-\r
- @param[in] Count The number of memory operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
-\r
- @param[out] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMemRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root\r
- bridge memory space.\r
-\r
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r
- controller registers in the PCI root bridge memory space.\r
- The memory operations are carried out exactly as requested. The caller is\r
- responsible for satisfying any alignment and memory width restrictions that a\r
- PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operation.\r
-\r
- @param[in] Address The base address of the memory operation. The caller\r
- is responsible for aligning the Address if required.\r
-\r
- @param[in] Count The number of memory operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
-\r
- @param[in] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMemWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root\r
- bridge I/O space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] Address The base address of the I/O operation. The caller is\r
- responsible for aligning the Address if required.\r
-\r
- @param[in] Count The number of I/O operations to perform. Bytes moved\r
- is Width size * Count, starting at Address.\r
-\r
- @param[out] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoIoRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root\r
- bridge I/O space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] Address The base address of the I/O operation. The caller is\r
- responsible for aligning the Address if required.\r
-\r
- @param[in] Count The number of I/O operations to perform. Bytes moved\r
- is Width size * Count, starting at Address.\r
-\r
- @param[in] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoIoWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to copy one region of PCI root bridge memory space to\r
- another region of PCI root bridge memory space.\r
-\r
- The CopyMem() function enables a PCI driver to copy one region of PCI root\r
- bridge memory space to another region of PCI root bridge memory space. This\r
- is especially useful for video scroll operation on a memory mapped video\r
- buffer.\r
- The memory operations are carried out exactly as requested. The caller is\r
- responsible for satisfying any alignment and memory width restrictions that a\r
- PCI root bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
- instance.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] DestAddress The destination address of the memory operation. The\r
- caller is responsible for aligning the DestAddress if\r
- required.\r
-\r
- @param[in] SrcAddress The source address of the memory operation. The caller\r
- is responsible for aligning the SrcAddress if\r
- required.\r
-\r
- @param[in] Count The number of memory operations to perform. Bytes\r
- moved is Width size * Count, starting at DestAddress\r
- and SrcAddress.\r
-\r
- @retval EFI_SUCCESS The data was copied from one memory region\r
- to another memory region.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoCopyMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 DestAddress,\r
- IN UINT64 SrcAddress,\r
- IN UINTN Count\r
- )\r
-{\r
- EFI_STATUS Status;\r
- BOOLEAN Direction;\r
- UINTN Stride;\r
- UINTN Index;\r
- UINT64 Result;\r
-\r
- if ((UINT32)Width > EfiPciWidthUint64) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if (DestAddress == SrcAddress) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- Stride = (UINTN)(1 << Width);\r
-\r
- Direction = TRUE;\r
- if ((DestAddress > SrcAddress) &&\r
- (DestAddress < (SrcAddress + Count * Stride))) {\r
- Direction = FALSE;\r
- SrcAddress = SrcAddress + (Count-1) * Stride;\r
- DestAddress = DestAddress + (Count-1) * Stride;\r
- }\r
-\r
- for (Index = 0;Index < Count;Index++) {\r
- Status = RootBridgeIoMemRead (\r
- This,\r
- Width,\r
- SrcAddress,\r
- 1,\r
- &Result\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- Status = RootBridgeIoMemWrite (\r
- This,\r
- Width,\r
- DestAddress,\r
- 1,\r
- &Result\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- if (Direction) {\r
- SrcAddress += Stride;\r
- DestAddress += Stride;\r
- } else {\r
- SrcAddress -= Stride;\r
- DestAddress -= Stride;\r
- }\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in a PCI root\r
- bridge's configuration space.\r
-\r
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI\r
- configuration registers for a PCI controller.\r
- The PCI Configuration operations are carried out exactly as requested. The\r
- caller is responsible for any alignment and PCI configuration width issues\r
- that a PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] Address The address within the PCI configuration space for the\r
- PCI controller.\r
-\r
- @param[in] Count The number of PCI configuration operations to perform.\r
- Bytes moved is Width size * Count, starting at\r
- Address.\r
-\r
- @param[out] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPciRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in a PCI root\r
- bridge's configuration space.\r
-\r
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI\r
- configuration registers for a PCI controller.\r
- The PCI Configuration operations are carried out exactly as requested. The\r
- caller is responsible for any alignment and PCI configuration width issues\r
- that a PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Width Signifies the width of the memory operations.\r
-\r
- @param[in] Address The address within the PCI configuration space for the\r
- PCI controller.\r
-\r
- @param[in] Count The number of PCI configuration operations to perform.\r
- Bytes moved is Width size * Count, starting at\r
- Address.\r
-\r
- @param[in] Buffer For read operations, the destination buffer to store\r
- the results. For write operations, the source buffer\r
- to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI\r
- root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
-\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPciWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Provides the PCI controller-specific addresses required to access system\r
- memory from a DMA bus master.\r
-\r
- The Map() function provides the PCI controller specific addresses needed to\r
- access system memory. This function is used to map system memory for PCI bus\r
- master DMA accesses.\r
-\r
- @param[in] This A pointer to the\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Operation Indicates if the bus master is going to read\r
- or write to system memory.\r
-\r
- @param[in] HostAddress The system memory address to map to the PCI\r
- controller.\r
-\r
- @param[in, out] NumberOfBytes On input the number of bytes to map. On\r
- output the number of bytes that were mapped.\r
-\r
- @param[out] DeviceAddress The resulting map address for the bus master\r
- PCI controller to use to access the system\r
- memory's HostAddress.\r
-\r
- @param[out] Mapping The value to pass to Unmap() when the bus\r
- master DMA operation is complete.\r
-\r
- @retval EFI_SUCCESS The range was mapped for the returned\r
- NumberOfBytes.\r
-\r
- @retval EFI_INVALID_PARAMETER Operation is invalid.\r
-\r
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
-\r
- @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.\r
-\r
- @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.\r
-\r
- @retval EFI_INVALID_PARAMETER Mapping is NULL.\r
-\r
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common\r
- buffer.\r
-\r
- @retval EFI_DEVICE_ERROR The system hardware could not map the\r
- requested address.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
- lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
- IN VOID *HostAddress,\r
- IN OUT UINTN *NumberOfBytes,\r
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
- OUT VOID **Mapping\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
- MAP_INFO *MapInfo;\r
-\r
- if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||\r
- Mapping == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Initialize the return values to their defaults\r
- //\r
- *Mapping = NULL;\r
-\r
- //\r
- // Make sure that Operation is valid\r
- //\r
- if ((UINT32)Operation >= EfiPciOperationMaximum) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Most PCAT like chipsets can not handle performing DMA above 4GB.\r
- // If any part of the DMA transfer being mapped is above 4GB, then\r
- // map the DMA transfer to a buffer below 4GB.\r
- //\r
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;\r
- if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) {\r
-\r
- //\r
- // Common Buffer operations can not be remapped. If the common buffer\r
- // if above 4GB, then it is not possible to generate a mapping, so return\r
- // an error.\r
- //\r
- if (Operation == EfiPciOperationBusMasterCommonBuffer ||\r
- Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r
- // called later.\r
- //\r
- Status = gBS->AllocatePool (\r
- EfiBootServicesData,\r
- sizeof(MAP_INFO),\r
- (VOID **)&MapInfo\r
- );\r
- if (EFI_ERROR (Status)) {\r
- *NumberOfBytes = 0;\r
- return Status;\r
- }\r
-\r
- //\r
- // Return a pointer to the MAP_INFO structure in Mapping\r
- //\r
- *Mapping = MapInfo;\r
-\r
- //\r
- // Initialize the MAP_INFO structure\r
- //\r
- MapInfo->Operation = Operation;\r
- MapInfo->NumberOfBytes = *NumberOfBytes;\r
- MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES(*NumberOfBytes);\r
- MapInfo->HostAddress = PhysicalAddress;\r
- MapInfo->MappedHostAddress = 0x00000000ffffffff;\r
-\r
- //\r
- // Allocate a buffer below 4GB to map the transfer to.\r
- //\r
- Status = gBS->AllocatePages (\r
- AllocateMaxAddress,\r
- EfiBootServicesData,\r
- MapInfo->NumberOfPages,\r
- &MapInfo->MappedHostAddress\r
- );\r
- if (EFI_ERROR (Status)) {\r
- gBS->FreePool (MapInfo);\r
- *NumberOfBytes = 0;\r
- return Status;\r
- }\r
-\r
- //\r
- // If this is a read operation from the Bus Master's point of view,\r
- // then copy the contents of the real buffer into the mapped buffer\r
- // so the Bus Master can read the contents of the real buffer.\r
- //\r
- if (Operation == EfiPciOperationBusMasterRead ||\r
- Operation == EfiPciOperationBusMasterRead64) {\r
- CopyMem (\r
- (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
- (VOID *)(UINTN)MapInfo->HostAddress,\r
- MapInfo->NumberOfBytes\r
- );\r
- }\r
-\r
- //\r
- // The DeviceAddress is the address of the maped buffer below 4GB\r
- //\r
- *DeviceAddress = MapInfo->MappedHostAddress;\r
- } else {\r
- //\r
- // The transfer is below 4GB, so the DeviceAddress is simply the\r
- // HostAddress\r
- //\r
- *DeviceAddress = PhysicalAddress;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Completes the Map() operation and releases any corresponding resources.\r
-\r
- The Unmap() function completes the Map() operation and releases any\r
- corresponding resources.\r
- If the operation was an EfiPciOperationBusMasterWrite or\r
- EfiPciOperationBusMasterWrite64, the data is committed to the target system\r
- memory.\r
- Any resources used for the mapping are freed.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Mapping The mapping value returned from Map().\r
-\r
- @retval EFI_SUCCESS The range was unmapped.\r
-\r
- @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by\r
- Map().\r
-\r
- @retval EFI_DEVICE_ERROR The data was not committed to the target\r
- system memory.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoUnmap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN VOID *Mapping\r
- )\r
-{\r
- MAP_INFO *MapInfo;\r
-\r
- //\r
- // See if the Map() operation associated with this Unmap() required a mapping\r
- // buffer. If a mapping buffer was not required, then this function simply\r
- // returns EFI_SUCCESS.\r
- //\r
- if (Mapping != NULL) {\r
- //\r
- // Get the MAP_INFO structure from Mapping\r
- //\r
- MapInfo = (MAP_INFO *)Mapping;\r
-\r
- //\r
- // If this is a write operation from the Bus Master's point of view,\r
- // then copy the contents of the mapped buffer into the real buffer\r
- // so the processor can read the contents of the real buffer.\r
- //\r
- if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||\r
- MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r
- CopyMem (\r
- (VOID *)(UINTN)MapInfo->HostAddress,\r
- (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
- MapInfo->NumberOfBytes\r
- );\r
- }\r
-\r
- //\r
- // Free the mapped buffer and the MAP_INFO structure.\r
- //\r
- gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r
- gBS->FreePool (Mapping);\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer\r
- or EfiPciOperationBusMasterCommonBuffer64 mapping.\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param Type This parameter is not used and must be ignored.\r
-\r
- @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
- EfiRuntimeServicesData.\r
-\r
- @param Pages The number of pages to allocate.\r
-\r
- @param HostAddress A pointer to store the base system memory address of the\r
- allocated range.\r
-\r
- @param Attributes The requested bit mask of attributes for the allocated\r
- range. Only the attributes\r
- EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,\r
- EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and\r
- EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this\r
- function.\r
-\r
- @retval EFI_SUCCESS The requested memory pages were allocated.\r
-\r
- @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r
-\r
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
-\r
- @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal\r
- attribute bits are MEMORY_WRITE_COMBINE,\r
- MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
-\r
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoAllocateBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_ALLOCATE_TYPE Type,\r
- IN EFI_MEMORY_TYPE MemoryType,\r
- IN UINTN Pages,\r
- OUT VOID **HostAddress,\r
- IN UINT64 Attributes\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
-\r
- //\r
- // Validate Attributes\r
- //\r
- if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // Check for invalid inputs\r
- //\r
- if (HostAddress == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // The only valid memory types are EfiBootServicesData and\r
- // EfiRuntimeServicesData\r
- //\r
- if (MemoryType != EfiBootServicesData &&\r
- MemoryType != EfiRuntimeServicesData) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Limit allocations to memory below 4GB\r
- //\r
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);\r
-\r
- Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages,\r
- &PhysicalAddress);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- *HostAddress = (VOID *)(UINTN)PhysicalAddress;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Frees memory that was allocated with AllocateBuffer().\r
-\r
- The FreeBuffer() function frees memory that was allocated with\r
- AllocateBuffer().\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param Pages The number of pages to free.\r
-\r
- @param HostAddress The base system memory address of the allocated range.\r
-\r
- @retval EFI_SUCCESS The requested memory pages were freed.\r
-\r
- @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and\r
- Pages was not allocated with AllocateBuffer().\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoFreeBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINTN Pages,\r
- OUT VOID *HostAddress\r
- )\r
-{\r
- return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);\r
-}\r
-\r
-/**\r
- Flushes all PCI posted write transactions from a PCI host bridge to system\r
- memory.\r
-\r
- The Flush() function flushes any PCI posted write transactions from a PCI\r
- host bridge to system memory. Posted write transactions are generated by PCI\r
- bus masters when they perform write transactions to target addresses in\r
- system memory.\r
- This function does not flush posted write transactions from any PCI bridges.\r
- A PCI controller specific action must be taken to guarantee that the posted\r
- write transactions have been flushed from the PCI controller and from all the\r
- PCI bridges into the PCI host bridge. This is typically done with a PCI read\r
- transaction from the PCI controller prior to calling Flush().\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @retval EFI_SUCCESS The PCI posted write transactions were flushed\r
- from the PCI host bridge to system memory.\r
-\r
- @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed\r
- from the PCI host bridge due to a hardware error.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoFlush (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
- )\r
-{\r
- //\r
- // not supported yet\r
- //\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Gets the attributes that a PCI root bridge supports setting with\r
- SetAttributes(), and the attributes that a PCI root bridge is currently\r
- using.\r
-\r
- The GetAttributes() function returns the mask of attributes that this PCI\r
- root bridge supports and the mask of attributes that the PCI root bridge is\r
- currently using.\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param Supported A pointer to the mask of attributes that this PCI root\r
- bridge supports setting with SetAttributes().\r
-\r
- @param Attributes A pointer to the mask of attributes that this PCI root\r
- bridge is currently using.\r
-\r
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes\r
- that the PCI root bridge supports is returned\r
- in Supports. If Attributes is not NULL, then\r
- the attributes that the PCI root bridge is\r
- currently using is returned in Attributes.\r
-\r
- @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoGetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT UINT64 *Supported,\r
- OUT UINT64 *Attributes\r
- )\r
-{\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
-\r
- if (Attributes == NULL && Supported == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Set the return value for Supported and Attributes\r
- //\r
- if (Supported != NULL) {\r
- *Supported = PrivateData->Supports;\r
- }\r
-\r
- if (Attributes != NULL) {\r
- *Attributes = PrivateData->Attributes;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Sets attributes for a resource range on a PCI root bridge.\r
-\r
- The SetAttributes() function sets the attributes specified in Attributes for\r
- the PCI root bridge on the resource range specified by ResourceBase and\r
- ResourceLength. Since the granularity of setting these attributes may vary\r
- from resource type to resource type, and from platform to platform, the\r
- actual resource range and the one passed in by the caller may differ. As a\r
- result, this function may set the attributes specified by Attributes on a\r
- larger resource range than the caller requested. The actual range is returned\r
- in ResourceBase and ResourceLength. The caller is responsible for verifying\r
- that the actual range for which the attributes were set is acceptable.\r
-\r
- @param[in] This A pointer to the\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[in] Attributes The mask of attributes to set. If the\r
- attribute bit MEMORY_WRITE_COMBINE,\r
- MEMORY_CACHED, or MEMORY_DISABLE is set,\r
- then the resource range is specified by\r
- ResourceBase and ResourceLength. If\r
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
- MEMORY_DISABLE are not set, then\r
- ResourceBase and ResourceLength are ignored,\r
- and may be NULL.\r
-\r
- @param[in, out] ResourceBase A pointer to the base address of the\r
- resource range to be modified by the\r
- attributes specified by Attributes.\r
-\r
- @param[in, out] ResourceLength A pointer to the length of the resource\r
- range to be modified by the attributes\r
- specified by Attributes.\r
-\r
- @retval EFI_SUCCESS The current configuration of this PCI root bridge\r
- was returned in Resources.\r
-\r
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge\r
- could not be retrieved.\r
-\r
- @retval EFI_INVALID_PARAMETER Invalid pointer of\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoSetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINT64 Attributes,\r
- IN OUT UINT64 *ResourceBase,\r
- IN OUT UINT64 *ResourceLength\r
- )\r
-{\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
-\r
- if (Attributes != 0) {\r
- if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- //\r
- // This is a generic driver for a PC-AT class system. It does not have any\r
- // chipset specific knowlegde, so none of the attributes can be set or\r
- // cleared. Any attempt to set attribute that are already set will succeed,\r
- // and any attempt to set an attribute that is not supported will fail.\r
- //\r
- if (Attributes & (~PrivateData->Attributes)) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Retrieves the current resource settings of this PCI root bridge in the form\r
- of a set of ACPI 2.0 resource descriptors.\r
-\r
- There are only two resource descriptor types from the ACPI Specification that\r
- may be used to describe the current resources allocated to a PCI root bridge.\r
- These are the QWORD Address Space Descriptor (ACPI 2.0 Section 6.4.3.5.1),\r
- and the End Tag (ACPI 2.0 Section 6.4.2.8). The QWORD Address Space\r
- Descriptor can describe memory, I/O, and bus number ranges for dynamic or\r
- fixed resources. The configuration of a PCI root bridge is described with one\r
- or more QWORD Address Space Descriptors followed by an End Tag.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that\r
- describe the current configuration of this PCI root\r
- bridge. The storage for the ACPI 2.0 resource\r
- descriptors is allocated by this function. The\r
- caller must treat the return buffer as read-only\r
- data, and the buffer must not be freed by the\r
- caller.\r
-\r
- @retval EFI_SUCCESS The current configuration of this PCI root bridge\r
- was returned in Resources.\r
-\r
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge\r
- could not be retrieved.\r
-\r
- @retval EFI_INVALID_PARAMETER Invalid pointer of\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoConfiguration (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT VOID **Resources\r
- )\r
-{\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- UINTN Index;\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
-\r
- for (Index = 0; Index < TypeMax; Index++) {\r
- if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;\r
-\r
- Desc = &Configuration.SpaceDesp[Index];\r
- Desc->AddrRangeMin = PrivateData->ResAllocNode[Index].Base;\r
- Desc->AddrRangeMax = PrivateData->ResAllocNode[Index].Base +\r
- PrivateData->ResAllocNode[Index].Length - 1;\r
- Desc->AddrLen = PrivateData->ResAllocNode[Index].Length;\r
- }\r
- }\r
-\r
- *Resources = &Configuration;\r
- return EFI_SUCCESS;\r
-}\r
-\r
projects / mirror_edk2.git / blobdiff