\r
RESOURCE_CONFIGURATION Configuration = {\r
{{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0}, \r
+ {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},\r
{0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},\r
{0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},\r
{0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},\r
**/\r
EFI_STATUS\r
EFIAPI\r
-RootBridgeIoPollMem ( \r
+RootBridgeIoPollMem (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
**/\r
EFI_STATUS\r
EFIAPI\r
-RootBridgeIoPollIo ( \r
+RootBridgeIoPollIo (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN UINT64 Attributes,\r
IN OUT UINT64 *ResourceBase,\r
- IN OUT UINT64 *ResourceLength \r
- ); \r
+ IN OUT UINT64 *ResourceLength\r
+ );\r
\r
/**\r
Retrieves the current resource settings of this PCI root bridge in the form\r
//\r
PrivateData->BusBase = ResAperture->BusBase;\r
PrivateData->BusLimit = ResAperture->BusLimit;\r
- \r
+\r
//\r
// Specific for this chipset\r
//\r
PrivateData->ResAllocNode[Index].Length = 0;\r
PrivateData->ResAllocNode[Index].Status = ResNone;\r
}\r
- \r
+\r
PrivateData->RootBridgeAttrib = Attri;\r
- \r
- PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \\r
- EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \\r
- EFI_PCI_ATTRIBUTE_VGA_MEMORY | \\r
- EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+\r
+ PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
+ EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
PrivateData->Attributes = PrivateData->Supports;\r
\r
Protocol->ParentHandle = HostBridgeHandle;\r
- \r
+\r
Protocol->PollMem = RootBridgeIoPollMem;\r
Protocol->PollIo = RootBridgeIoPollIo;\r
\r
\r
Protocol->SegmentNumber = 0;\r
\r
- Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);\r
+ Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL,\r
+ (VOID **)&mMetronome);\r
ASSERT_EFI_ERROR (Status);\r
\r
return EFI_SUCCESS;\r
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
\r
//\r
- // Check to see if any address associated with this transfer exceeds the maximum \r
- // allowed address. The maximum address implied by the parameters passed in is\r
- // Address + Size * Count. If the following condition is met, then the transfer\r
- // is not supported.\r
+ // Check to see if any address associated with this transfer exceeds the\r
+ // maximum allowed address. The maximum address implied by the parameters\r
+ // passed in is Address + Size * Count. If the following condition is met,\r
+ // then the transfer is not supported.\r
//\r
// Address + Size * Count > Limit + 1\r
//\r
- // Since Limit can be the maximum integer value supported by the CPU and Count \r
- // can also be the maximum integer value supported by the CPU, this range\r
- // check must be adjusted to avoid all oveflow conditions.\r
- // \r
- // The following form of the range check is equivalent but assumes that \r
+ // Since Limit can be the maximum integer value supported by the CPU and\r
+ // Count can also be the maximum integer value supported by the CPU, this\r
+ // range check must be adjusted to avoid all oveflow conditions.\r
+ //\r
+ // The following form of the range check is equivalent but assumes that\r
// Limit is of the form (2^n - 1).\r
//\r
if (OperationType == IoOperation) {\r
Limit = PrivateData->MemLimit;\r
} else {\r
PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
- if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {\r
+ if (PciRbAddr->Bus < PrivateData->BusBase ||\r
+ PciRbAddr->Bus > PrivateData->BusLimit) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {\r
+ if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER ||\r
+ PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if (Address > Limit) {\r
return EFI_UNSUPPORTED;\r
}\r
- } else { \r
+ } else {\r
MaxCount = RShiftU64 (Limit, Width);\r
if (MaxCount < (Count - 1)) {\r
return EFI_UNSUPPORTED;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
UINT8 *Uint8Buffer;\r
\r
- Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);\r
+ Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,\r
+ Count, Buffer);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
InStride = mInStride[Width];\r
OutStride = mOutStride[Width];\r
OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
+ for (Uint8Buffer = Buffer;\r
+ Count > 0;\r
+ Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (Write) {\r
switch (OperationWidth) {\r
case EfiPciWidthUint8:\r
}\r
}\r
}\r
- return EFI_SUCCESS; \r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
UINT8 *Uint8Buffer;\r
\r
- Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);\r
+ Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address,\r
+ Count, Buffer);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
}\r
#endif\r
\r
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
+ for (Uint8Buffer = Buffer;\r
+ Count > 0;\r
+ Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (Write) {\r
switch (OperationWidth) {\r
case EfiPciWidthUint8:\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r
UINTN PcieRegAddr;\r
\r
- Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);\r
+ Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address,\r
+ Count, Buffer);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
InStride = mInStride[Width];\r
OutStride = mOutStride[Width];\r
OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {\r
+ for (Uint8Buffer = Buffer;\r
+ Count > 0;\r
+ PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {\r
if (Write) {\r
switch (OperationWidth) {\r
case EfiPciWidthUint8:\r
**/\r
EFI_STATUS\r
EFIAPI\r
-RootBridgeIoPollMem ( \r
+RootBridgeIoPollMem (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
Status = This->Mem.Read (This, Width, Address, 1, Result);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
- } \r
+ }\r
if ((*Result & Mask) == Value) {\r
return EFI_SUCCESS;\r
}\r
\r
if (Delay == 0) {\r
return EFI_SUCCESS;\r
- \r
+\r
} else {\r
\r
//\r
// Determine the proper # of metronome ticks to wait for polling the\r
- // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
+ // location. The nuber of ticks is Roundup (Delay /\r
+ // mMetronome->TickPeriod)+1\r
// The "+1" to account for the possibility of the first tick being short\r
// because we started in the middle of a tick.\r
//\r
// BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome\r
// protocol definition is updated.\r
//\r
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);\r
+ NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod,\r
+ &Remainder);\r
if (Remainder != 0) {\r
NumberOfTicks += 1;\r
}\r
NumberOfTicks += 1;\r
- \r
+\r
while (NumberOfTicks != 0) {\r
\r
mMetronome->WaitForTick (mMetronome, 1);\r
- \r
+\r
Status = This->Mem.Read (This, Width, Address, 1, Result);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- \r
+\r
if ((*Result & Mask) == Value) {\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
EFIAPI\r
-RootBridgeIoPollIo ( \r
+RootBridgeIoPollIo (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
if ((UINT32)Width > EfiPciWidthUint64) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
Status = This->Io.Read (This, Width, Address, 1, Result);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
- } \r
+ }\r
if ((*Result & Mask) == Value) {\r
return EFI_SUCCESS;\r
}\r
\r
if (Delay == 0) {\r
return EFI_SUCCESS;\r
- \r
+\r
} else {\r
\r
//\r
// Determine the proper # of metronome ticks to wait for polling the\r
- // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
+ // location. The number of ticks is Roundup (Delay /\r
+ // mMetronome->TickPeriod)+1\r
// The "+1" to account for the possibility of the first tick being short\r
// because we started in the middle of a tick.\r
//\r
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);\r
+ NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod,\r
+ &Remainder);\r
if (Remainder != 0) {\r
NumberOfTicks += 1;\r
}\r
NumberOfTicks += 1;\r
- \r
+\r
while (NumberOfTicks != 0) {\r
\r
mMetronome->WaitForTick (mMetronome, 1);\r
- \r
+\r
Status = This->Io.Read (This, Width, Address, 1, Result);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- \r
+\r
if ((*Result & Mask) == Value) {\r
return EFI_SUCCESS;\r
}\r
IN VOID *Buffer\r
)\r
{\r
- return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer); \r
+ return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
OUT VOID *Buffer\r
)\r
{\r
- return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer); \r
+ return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
IN VOID *Buffer\r
)\r
{\r
- return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer); \r
+ return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
\r
if ((UINT32)Width > EfiPciWidthUint64) {\r
return EFI_INVALID_PARAMETER;\r
- } \r
+ }\r
\r
if (DestAddress == SrcAddress) {\r
return EFI_SUCCESS;\r
Stride = (UINTN)(1 << Width);\r
\r
Direction = TRUE;\r
- if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {\r
+ if ((DestAddress > SrcAddress) &&\r
+ (DestAddress < (SrcAddress + Count * Stride))) {\r
Direction = FALSE;\r
SrcAddress = SrcAddress + (Count-1) * Stride;\r
DestAddress = DestAddress + (Count-1) * Stride;\r
EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
MAP_INFO *MapInfo;\r
\r
- if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r
+ if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||\r
+ Mapping == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
// Initialize the return values to their defaults\r
//\r
\r
//\r
// Common Buffer operations can not be remapped. If the common buffer\r
- // if above 4GB, then it is not possible to generate a mapping, so return \r
+ // if above 4GB, then it is not possible to generate a mapping, so return\r
// an error.\r
//\r
- if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
+ if (Operation == EfiPciOperationBusMasterCommonBuffer ||\r
+ Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
// called later.\r
//\r
Status = gBS->AllocatePool (\r
- EfiBootServicesData, \r
- sizeof(MAP_INFO), \r
+ EfiBootServicesData,\r
+ sizeof(MAP_INFO),\r
(VOID **)&MapInfo\r
);\r
if (EFI_ERROR (Status)) {\r
// Allocate a buffer below 4GB to map the transfer to.\r
//\r
Status = gBS->AllocatePages (\r
- AllocateMaxAddress, \r
- EfiBootServicesData, \r
+ AllocateMaxAddress,\r
+ EfiBootServicesData,\r
MapInfo->NumberOfPages,\r
&MapInfo->MappedHostAddress\r
);\r
// then copy the contents of the real buffer into the mapped buffer\r
// so the Bus Master can read the contents of the real buffer.\r
//\r
- if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {\r
+ if (Operation == EfiPciOperationBusMasterRead ||\r
+ Operation == EfiPciOperationBusMasterRead64) {\r
CopyMem (\r
- (VOID *)(UINTN)MapInfo->MappedHostAddress, \r
+ (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
(VOID *)(UINTN)MapInfo->HostAddress,\r
MapInfo->NumberOfBytes\r
);\r
*DeviceAddress = MapInfo->MappedHostAddress;\r
} else {\r
//\r
- // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress\r
+ // The transfer is below 4GB, so the DeviceAddress is simply the\r
+ // HostAddress\r
//\r
*DeviceAddress = PhysicalAddress;\r
}\r
MAP_INFO *MapInfo;\r
\r
//\r
- // See if the Map() operation associated with this Unmap() required a mapping buffer.\r
- // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.\r
+ // See if the Map() operation associated with this Unmap() required a mapping\r
+ // buffer. If a mapping buffer was not required, then this function simply\r
+ // returns EFI_SUCCESS.\r
//\r
if (Mapping != NULL) {\r
//\r
// then copy the contents of the mapped buffer into the real buffer\r
// so the processor can read the contents of the real buffer.\r
//\r
- if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r
+ if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||\r
+ MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r
CopyMem (\r
- (VOID *)(UINTN)MapInfo->HostAddress, \r
+ (VOID *)(UINTN)MapInfo->HostAddress,\r
(VOID *)(UINTN)MapInfo->MappedHostAddress,\r
MapInfo->NumberOfBytes\r
);\r
if (HostAddress == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
- // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData\r
+ // The only valid memory types are EfiBootServicesData and\r
+ // EfiRuntimeServicesData\r
//\r
- if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {\r
+ if (MemoryType != EfiBootServicesData &&\r
+ MemoryType != EfiRuntimeServicesData) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);\r
\r
- Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);\r
+ Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages,\r
+ &PhysicalAddress);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
// Set the return value for Supported and Attributes\r
//\r
if (Supported != NULL) {\r
- *Supported = PrivateData->Supports; \r
+ *Supported = PrivateData->Supports;\r
}\r
\r
if (Attributes != NULL) {\r
*Attributes = PrivateData->Attributes;\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN UINT64 Attributes,\r
IN OUT UINT64 *ResourceBase,\r
- IN OUT UINT64 *ResourceLength \r
+ IN OUT UINT64 *ResourceLength\r
)\r
{\r
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- \r
+\r
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
- \r
+\r
if (Attributes != 0) {\r
if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
return EFI_UNSUPPORTED;\r
}\r
}\r
- \r
+\r
//\r
// This is a generic driver for a PC-AT class system. It does not have any\r
- // chipset specific knowlegde, so none of the attributes can be set or \r
- // cleared. Any attempt to set attribute that are already set will succeed, \r
+ // chipset specific knowlegde, so none of the attributes can be set or\r
+ // cleared. Any attempt to set attribute that are already set will succeed,\r
// and any attempt to set an attribute that is not supported will fail.\r
//\r
if (Attributes & (~PrivateData->Attributes)) {\r
UINTN Index;\r
\r
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
- \r
+\r
for (Index = 0; Index < TypeMax; Index++) {\r
if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {\r
- Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;\r
- Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;\r
- Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;\r
- } \r
- } \r
- \r
- *Resources = &Configuration; \r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;\r
+\r
+ Desc = &Configuration.SpaceDesp[Index];\r
+ Desc->AddrRangeMin = PrivateData->ResAllocNode[Index].Base;\r
+ Desc->AddrRangeMax = PrivateData->ResAllocNode[Index].Base +\r
+ PrivateData->ResAllocNode[Index].Length - 1;\r
+ Desc->AddrLen = PrivateData->ResAllocNode[Index].Length;\r
+ }\r
+ }\r
+\r
+ *Resources = &Configuration;\r
return EFI_SUCCESS;\r
}\r
\r
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