+++ /dev/null
-/** @file\r
- Generic definitions for registers in the Intel Ich devices.\r
-\r
- These definitions should work for any version of Ich.\r
-\r
- Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef _GENERIC_ICH_H_\r
-#define _GENERIC_ICH_H_\r
-\r
-/** GenericIchDefs Generic ICH Definitions.\r
-\r
-Definitions beginning with "R_" are registers.\r
-Definitions beginning with "B_" are bits within registers.\r
-Definitions beginning with "V_" are meaningful values of bits within the registers.\r
-**/\r
-///@{\r
-\r
-/// IchPciAddressing PCI Bus Address for ICH.\r
-///@{\r
-#define PCI_BUS_NUMBER_ICH 0x00 ///< ICH is on PCI Bus 0.\r
-#define PCI_DEVICE_NUMBER_ICH_LPC 31 ///< ICH is Device 31.\r
-#define PCI_FUNCTION_NUMBER_ICH_LPC 0 ///< ICH is Function 0.\r
-///@}\r
-\r
-/// IchAcpiCntr Control for the ICH's ACPI Counter.\r
-///@{\r
-#define R_ICH_LPC_ACPI_BASE 0x40\r
-#define B_ICH_LPC_ACPI_BASE_BAR 0x0000FF80\r
-#define R_ICH_LPC_ACPI_CNT 0x44\r
-#define B_ICH_LPC_ACPI_CNT_ACPI_EN 0x80\r
-///@}\r
-\r
-/// IchAcpiTimer The ICH's ACPI Timer.\r
-///@{\r
-#define R_ACPI_PM1_TMR 0x08\r
-#define V_ACPI_TMR_FREQUENCY 3579545\r
-#define V_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow.\r
-///@}\r
-\r
-/// Macro to generate the PCI address of any given ICH Register.\r
-#define PCI_ICH_LPC_ADDRESS(Register) \\r
- ((UINTN)(PCI_LIB_ADDRESS (PCI_BUS_NUMBER_ICH, PCI_DEVICE_NUMBER_ICH_LPC, PCI_FUNCTION_NUMBER_ICH_LPC, Register)))\r
-\r
-///@}\r
-#endif // _GENERIC_ICH_H_\r