--- /dev/null
+/** @file\r
+Memory controller configuration.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#ifndef __DDR_MEMORY_CONTROLLER_H__\r
+#define __DDR_MEMORY_CONTROLLER_H__\r
+\r
+//\r
+// DDR timing data definitions.\r
+// These are used to create bitmaps of valid timing configurations.\r
+//\r
+\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN 0xFF\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF\r
+\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20 0x01\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25 0x00\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30 0x02\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL 0x03\r
+\r
+\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02 0x02\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03 0x01\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04 0x00\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL 0x03\r
+\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02 0x02\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03 0x01\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04 0x00\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL 0x03\r
+\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05 0x05\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06 0x04\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07 0x03\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08 0x02\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09 0x01\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10 0x00\r
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL 0x07\r
+\r
+#define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED 0x01\r
+#define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED 0x02\r
+#define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED 0x04\r
+#define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED 0x08\r
+#define DUAL_CHANNEL_DDR_DATA_TYPE_SDR 0x10\r
+#define DUAL_CHANNEL_DDR_DATA_TYPE_DDR 0x20\r
+\r
+\r
+//\r
+// Maximum number of SDRAM channels supported by the memory controller\r
+//\r
+#define MAX_CHANNELS 1\r
+\r
+//\r
+// Maximum number of DIMM sockets supported by the memory controller\r
+//\r
+#define MAX_SOCKETS 1\r
+\r
+//\r
+// Maximum number of sides supported per DIMM\r
+//\r
+#define MAX_SIDES 2\r
+\r
+//\r
+// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
+// DIMM's from the various channels\r
+//\r
+#define MAX_SOCKET_SETS 2\r
+\r
+//\r
+// Maximum number of rows supported by the memory controller\r
+//\r
+#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)\r
+\r
+//\r
+// Maximum number of memory ranges supported by the memory controller\r
+//\r
+#define MAX_RANGES (MAX_ROWS + 5)\r
+\r
+//\r
+// Maximum Number of Log entries\r
+//\r
+#define MEMORY_LOG_MAX_INDEX 16\r
+\r
+\r
+typedef struct _MEMORY_LOG_ENTRY {\r
+ EFI_STATUS_CODE_VALUE Event;\r
+ EFI_STATUS_CODE_TYPE Severity;\r
+ UINT8 Data;\r
+} MEMORY_LOG_ENTRY;\r
+\r
+typedef struct _MEMORY_LOG {\r
+ UINT8 Index;\r
+ MEMORY_LOG_ENTRY Entry[MEMORY_LOG_MAX_INDEX];\r
+} MEMORY_LOG;\r
+\r
+\r
+\r
+//\r
+// Defined ECC types\r
+//\r
+#define DUAL_CHANNEL_DDR_ECC_TYPE_NONE 0x01 // No error checking\r
+#define DUAL_CHANNEL_DDR_ECC_TYPE_EC 0x02 // Error checking only\r
+#define DUAL_CHANNEL_DDR_ECC_TYPE_SECC 0x04 // Software Scrubbing ECC\r
+#define DUAL_CHANNEL_DDR_ECC_TYPE_HECC 0x08 // Hardware Scrubbing ECC\r
+#define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC 0x10 // Chip Kill ECC\r
+\r
+//\r
+// Row configuration status values\r
+//\r
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS 0x00 // No error\r
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN 0x01 // Pattern mismatch, no memory\r
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED 0x02 // Memory type not supported\r
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR 0x03 // Row/Col/Bnk mismatch\r
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR 0x04 // Received ECC error\r
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT 0x05 // Row is not present\r
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED 0x06 // Row is disabled\r
+\r
+\r
+//\r
+// Memory range types\r
+//\r
+typedef enum {\r
+ DualChannelDdrMainMemory,\r
+ DualChannelDdrSmramCacheable,\r
+ DualChannelDdrSmramNonCacheable,\r
+ DualChannelDdrGraphicsMemoryCacheable,\r
+ DualChannelDdrGraphicsMemoryNonCacheable,\r
+ DualChannelDdrReservedMemory,\r
+ DualChannelDdrMaxMemoryRangeType\r
+} DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
+\r
+//\r
+// Memory map range information\r
+//\r
+typedef struct {\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+ EFI_PHYSICAL_ADDRESS CpuAddress;\r
+ EFI_PHYSICAL_ADDRESS RangeLength;\r
+ DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;\r
+} DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
+typedef struct {\r
+ unsigned dramType :1; /**< Type: 0 = RESERVED; 1 = DDR2 */\r
+ unsigned dramWidth :1; /**< Width: 0 = x8; 1 = x16 */\r
+ unsigned dramDensity :2; /**< Density: 00b = 2Gb; 01b = 1Gb; 10b = 512Mb; 11b = 256Mb */\r
+ unsigned dramSpeed :1; /**< Speed Grade: 0 = RESERVED; 1 = 800MT/s;*/\r
+ unsigned dramTimings :3; /**< Timings: 4-4-4, 5-5-5, 6-6-6 */\r
+ unsigned dramRanks :1; /**< Ranks: 0 = Single Rank; 1 = Dual Rank */\r
+} DramGeometry; /**< DRAM Geometry Descriptor */\r
+\r
+typedef union _RegDRP {\r
+ UINT32 raw;\r
+ struct {\r
+ unsigned rank0Enabled :1; /**< Rank 0 Enable */\r
+ unsigned rank0DevWidth :2; /**< DRAM Device Width (x8,x16) */\r
+ unsigned rank0DevDensity :2; /**< DRAM Device Density (256Mb,512Mb,1Gb,2Gb) */\r
+ unsigned reserved2 :1;\r
+ unsigned rank1Enabled :1; /**< Rank 1 Enable */\r
+ unsigned reserved3 :5;\r
+ unsigned dramType :1; /**< DRAM Type (0=DDR2) */\r
+ unsigned reserved4 :5;\r
+ unsigned reserved5 :14;\r
+ } field;\r
+} RegDRP; /**< DRAM Rank Population and Interface Register */\r
+\r
+\r
+typedef union {\r
+ UINT32 raw;\r
+ struct {\r
+ unsigned dramFrequency :3; /**< DRAM Frequency (000=RESERVED,010=667,011=800) */\r
+ unsigned tRP :2; /**< Precharge to Activate Delay (3,4,5,6) */\r
+ unsigned reserved1 :1;\r
+ unsigned tRCD :2; /**< Activate to CAS Delay (3,4,5,6) */\r
+ unsigned reserved2 :1;\r
+ unsigned tCL :2; /**< CAS Latency (3,4,5,6) */\r
+ unsigned reserved3 :21;\r
+ } field;\r
+} RegDTR0; /**< DRAM Timing Register 0 */\r
+\r
+typedef union {\r
+ UINT32 raw;\r
+ struct {\r
+ unsigned tWRRD_dly :2; /**< Additional Write to Read Delay (0,1,2,3) */\r
+ unsigned reserved1 :1;\r
+ unsigned tRDWR_dly :2; /**< Additional Read to Write Delay (0,1,2,3) */\r
+ unsigned reserved2 :1;\r
+ unsigned tRDRD_dr_dly :1; /**< Additional Read to Read Delay (1,2) */\r
+ unsigned reserved3 :1;\r
+ unsigned tRD_dly :3; /**< Additional Read Data Sampling Delay (0-7) */\r
+ unsigned reserved4 :1;\r
+ unsigned tRCVEN_halfclk_dly :4; /**< Additional RCVEN Half Clock Delay Control */\r
+ unsigned reserved5 :1;\r
+ unsigned readDqDelay :2; /**< Read DQ Delay */\r
+ unsigned reserved6 :13;\r
+ } field;\r
+} RegDTR1; /**< DRAM Timing Register 1 */\r
+\r
+typedef union {\r
+ UINT32 raw;\r
+ struct {\r
+ unsigned ckStaticDisable :1; /**< CK/CK# Static Disable */\r
+ unsigned reserved1 :3;\r
+ unsigned ckeStaticDisable :2; /**< CKE Static Disable */\r
+ unsigned reserved2 :8;\r
+ unsigned refreshPeriod :2; /**< Refresh Period (disabled,128clks,3.9us,7.8us) */\r
+ unsigned refreshQueueDepth :2; /**< Refresh Queue Depth (1,2,4,8) */\r
+ unsigned reserved5 :13;\r
+ unsigned initComplete :1; /**< Initialization Complete */\r
+ } field;\r
+} RegDCO;\r
+\r
+//\r
+// MRC Data Structure\r
+//\r
+typedef struct {\r
+ RegDRP drp;\r
+ RegDTR0 dtr0;\r
+ RegDTR1 dtr1;\r
+ RegDCO dco;\r
+ UINT32 reg0104;\r
+ UINT32 reg0120;\r
+ UINT32 reg0121;\r
+ UINT32 reg0123;\r
+ UINT32 reg0111;\r
+ UINT32 reg0130;\r
+ UINT8 refreshPeriod; /**< Placeholder for the chosen refresh\r
+ * period. This value will NOT be\r
+ * programmed into DCO until all\r
+ * initialization is done.\r
+ */\r
+ UINT8 ddr2Odt; /**< 0 = Disabled, 1 = 75 ohm, 2 = 150ohm, 3 = 50ohm */\r
+ UINT8 sku; /**< Detected QuarkNcSocId SKU */\r
+ UINT8 capabilities; /**< Capabilities Available on this part */\r
+ UINT8 state; /**< NORMAL_BOOT, S3_RESUME */\r
+ UINT32 memSize; /**< Memory size */\r
+ UINT16 pmBase; /**< PM Base */\r
+ UINT16 mrcVersion; /**< MRC Version */\r
+ UINT32 hecbase; /**< HECBASE shifted left 16 bits */\r
+ DramGeometry geometry; /**< DRAM Geometry */\r
+} MRC_DATA_STRUCTURE; /**< QuarkNcSocId Memory Parameters for MRC */\r
+\r
+typedef struct _EFI_MEMINIT_CONFIG_DATA {\r
+ MRC_DATA_STRUCTURE MrcData;\r
+} EFI_MEMINIT_CONFIG_DATA;\r
+\r
+\r
+\r
+#endif\r
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