--- /dev/null
+/** @file\r
+This header file provides common definitions just for MCH using to avoid including extra module's file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _QNC_COMMON_DEFINITIONS_H_\r
+#define _QNC_COMMON_DEFINITIONS_H_\r
+\r
+//\r
+// PCI CONFIGURATION MAP REGISTER OFFSETS\r
+//\r
+#ifndef PCI_VID\r
+#define PCI_VID 0x0000 // Vendor ID Register\r
+#define PCI_DID 0x0002 // Device ID Register\r
+#define PCI_CMD 0x0004 // PCI Command Register\r
+#define PCI_STS 0x0006 // PCI Status Register\r
+#define PCI_RID 0x0008 // Revision ID Register\r
+#define PCI_IFT 0x0009 // Interface Type\r
+#define PCI_SCC 0x000A // Sub Class Code Register\r
+#define PCI_BCC 0x000B // Base Class Code Register\r
+#define PCI_CLS 0x000C // Cache Line Size\r
+#define PCI_PMLT 0x000D // Primary Master Latency Timer\r
+#define PCI_HDR 0x000E // Header Type Register\r
+#define PCI_BIST 0x000F // Built in Self Test Register\r
+#define PCI_BAR0 0x0010 // Base Address Register 0\r
+#define PCI_BAR1 0x0014 // Base Address Register 1\r
+#define PCI_BAR2 0x0018 // Base Address Register 2\r
+#define PCI_PBUS 0x0018 // Primary Bus Number Register\r
+#define PCI_SBUS 0x0019 // Secondary Bus Number Register\r
+#define PCI_SUBUS 0x001A // Subordinate Bus Number Register\r
+#define PCI_SMLT 0x001B // Secondary Master Latency Timer\r
+#define PCI_BAR3 0x001C // Base Address Register 3\r
+#define PCI_IOBASE 0x001C // I/O base Register\r
+#define PCI_IOLIMIT 0x001D // I/O Limit Register\r
+#define PCI_SECSTATUS 0x001E // Secondary Status Register\r
+#define PCI_BAR4 0x0020 // Base Address Register 4\r
+#define PCI_MEMBASE 0x0020 // Memory Base Register\r
+#define PCI_MEMLIMIT 0x0022 // Memory Limit Register\r
+#define PCI_BAR5 0x0024 // Base Address Register 5\r
+#define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register\r
+#define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register\r
+#define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits\r
+#define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits\r
+#define PCI_SVID 0x002C // Subsystem Vendor ID\r
+#define PCI_SID 0x002E // Subsystem ID\r
+#define PCI_IOBASE_U 0x0030 // I/O base Upper Register\r
+#define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register\r
+#define PCI_CAPP 0x0034 // Capabilities Pointer\r
+#define PCI_EROM 0x0038 // Expansion ROM Base Address\r
+#define PCI_INTLINE 0x003C // Interrupt Line Register\r
+#define PCI_INTPIN 0x003D // Interrupt Pin Register\r
+#define PCI_MAXGNT 0x003E // Max Grant Register\r
+#define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register\r
+#define PCI_MAXLAT 0x003F // Max Latency Register\r
+#endif\r
+//\r
+// Bit Difinitions\r
+//\r
+#ifndef BIT0\r
+#define BIT0 0x0001\r
+#define BIT1 0x0002\r
+#define BIT2 0x0004\r
+#define BIT3 0x0008\r
+#define BIT4 0x0010\r
+#define BIT5 0x0020\r
+#define BIT6 0x0040\r
+#define BIT7 0x0080\r
+#define BIT8 0x0100\r
+#define BIT9 0x0200\r
+#define BIT10 0x0400\r
+#define BIT11 0x0800\r
+#define BIT12 0x1000\r
+#define BIT13 0x2000\r
+#define BIT14 0x4000\r
+#define BIT15 0x8000\r
+#define BIT16 0x00010000\r
+#define BIT17 0x00020000\r
+#define BIT18 0x00040000\r
+#define BIT19 0x00080000\r
+#define BIT20 0x00100000\r
+#define BIT21 0x00200000\r
+#define BIT22 0x00400000\r
+#define BIT23 0x00800000\r
+#define BIT24 0x01000000\r
+#define BIT25 0x02000000\r
+#define BIT26 0x04000000\r
+#define BIT27 0x08000000\r
+#define BIT28 0x10000000\r
+#define BIT29 0x20000000\r
+#define BIT30 0x40000000\r
+#define BIT31 0x80000000\r
+#endif\r
+\r
+\r
+//\r
+// Common Memory mapped Io access macros ------------------------------------------\r
+//\r
+#define QNCMmioAddress( BaseAddr, Register ) \\r
+ ( (UINTN)BaseAddr + \\r
+ (UINTN)(Register) \\r
+ )\r
+\r
+//\r
+// UINT64\r
+//\r
+#define QNCMmio64Ptr( BaseAddr, Register ) \\r
+ ( (volatile UINT64 *)QNCMmioAddress( BaseAddr, Register ) )\r
+\r
+#define QNCMmio64( BaseAddr, Register ) \\r
+ *QNCMmio64Ptr( BaseAddr, Register )\r
+\r
+#define QNCMmio64Or( BaseAddr, Register, OrData ) \\r
+ QNCMmio64( BaseAddr, Register ) = \\r
+ (UINT64) ( \\r
+ QNCMmio64( BaseAddr, Register ) | \\r
+ (UINT64)(OrData) \\r
+ )\r
+\r
+#define QNCMmio64And( BaseAddr, Register, AndData ) \\r
+ QNCMmio64( BaseAddr, Register ) = \\r
+ (UINT64) ( \\r
+ QNCMmio64( BaseAddr, Register ) & \\r
+ (UINT64)(AndData) \\r
+ )\r
+\r
+#define QNCMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+ QNCMmio64( BaseAddr, Register ) = \\r
+ (UINT64) ( \\r
+ ( QNCMmio64( BaseAddr, Register ) & \\r
+ (UINT64)(AndData) \\r
+ ) | \\r
+ (UINT64)(OrData) \\r
+ )\r
+\r
+//\r
+// UINT32\r
+//\r
+#define QNCMmio32Ptr( BaseAddr, Register ) \\r
+ ( (volatile UINT32 *)QNCMmioAddress( BaseAddr, Register ) )\r
+\r
+#define QNCMmio32( BaseAddr, Register ) \\r
+ *QNCMmio32Ptr( BaseAddr, Register )\r
+\r
+#define QNCMmio32Or( BaseAddr, Register, OrData ) \\r
+ QNCMmio32( BaseAddr, Register ) = \\r
+ (UINT32) ( \\r
+ QNCMmio32( BaseAddr, Register ) | \\r
+ (UINT32)(OrData) \\r
+ )\r
+\r
+#define QNCMmio32And( BaseAddr, Register, AndData ) \\r
+ QNCMmio32( BaseAddr, Register ) = \\r
+ (UINT32) ( \\r
+ QNCMmio32( BaseAddr, Register ) & \\r
+ (UINT32)(AndData) \\r
+ )\r
+\r
+#define QNCMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+ QNCMmio32( BaseAddr, Register ) = \\r
+ (UINT32) ( \\r
+ ( QNCMmio32( BaseAddr, Register ) & \\r
+ (UINT32)(AndData) \\r
+ ) | \\r
+ (UINT32)(OrData) \\r
+ )\r
+//\r
+// UINT16\r
+//\r
+\r
+#define QNCMmio16Ptr( BaseAddr, Register ) \\r
+ ( (volatile UINT16 *)QNCMmioAddress( BaseAddr, Register ) )\r
+\r
+#define QNCMmio16( BaseAddr, Register ) \\r
+ *QNCMmio16Ptr( BaseAddr, Register )\r
+\r
+#define QNCMmio16Or( BaseAddr, Register, OrData ) \\r
+ QNCMmio16( BaseAddr, Register ) = \\r
+ (UINT16) ( \\r
+ QNCMmio16( BaseAddr, Register ) | \\r
+ (UINT16)(OrData) \\r
+ )\r
+\r
+#define QNCMmio16And( BaseAddr, Register, AndData ) \\r
+ QNCMmio16( BaseAddr, Register ) = \\r
+ (UINT16) ( \\r
+ QNCMmio16( BaseAddr, Register ) & \\r
+ (UINT16)(AndData) \\r
+ )\r
+\r
+#define QNCMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+ QNCMmio16( BaseAddr, Register ) = \\r
+ (UINT16) ( \\r
+ ( QNCMmio16( BaseAddr, Register ) & \\r
+ (UINT16)(AndData) \\r
+ ) | \\r
+ (UINT16)(OrData) \\r
+ )\r
+//\r
+// UINT8\r
+//\r
+#define QNCMmio8Ptr( BaseAddr, Register ) \\r
+ ( (volatile UINT8 *)QNCMmioAddress( BaseAddr, Register ) )\r
+\r
+#define QNCMmio8( BaseAddr, Register ) \\r
+ *QNCMmio8Ptr( BaseAddr, Register )\r
+\r
+#define QNCMmio8Or( BaseAddr, Register, OrData ) \\r
+ QNCMmio8( BaseAddr, Register ) = \\r
+ (UINT8) ( \\r
+ QNCMmio8( BaseAddr, Register ) | \\r
+ (UINT8)(OrData) \\r
+ )\r
+\r
+#define QNCMmio8And( BaseAddr, Register, AndData ) \\r
+ QNCMmio8( BaseAddr, Register ) = \\r
+ (UINT8) ( \\r
+ QNCMmio8( BaseAddr, Register ) & \\r
+ (UINT8)(AndData) \\r
+ )\r
+\r
+#define QNCMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+ QNCMmio8( BaseAddr, Register ) = \\r
+ (UINT8) ( \\r
+ ( QNCMmio8( BaseAddr, Register ) & \\r
+ (UINT8)(AndData) \\r
+ ) | \\r
+ (UINT8)(OrData) \\r
+ )\r
+\r
+//\r
+// Common Memory mapped Pci access macros ------------------------------------------\r
+//\r
+\r
+#define QNCMmPciAddress( Segment, Bus, Device, Function, Register ) \\r
+ ( (UINTN) QncGetPciExpressBaseAddress() + \\r
+ (UINTN)(Bus << 20) + \\r
+ (UINTN)(Device << 15) + \\r
+ (UINTN)(Function << 12) + \\r
+ (UINTN)(Register) \\r
+ )\r
+\r
+//\r
+// Macro to calculate the Pci device's base memory mapped address\r
+//\r
+#define PciDeviceMmBase( Bus, Device, Function) \\r
+ ( (UINTN) QncGetPciExpressBaseAddress () + \\r
+ (UINTN)(Bus << 20) + \\r
+ (UINTN)(Device << 15) + \\r
+ (UINTN)(Function << 12) \\r
+ )\r
+\r
+//\r
+// UINT32\r
+//\r
+#define QNCMmPci32Ptr( Segment, Bus, Device, Function, Register ) \\r
+ ( (volatile UINT32 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )\r
+\r
+#define QNCMmPci32( Segment, Bus, Device, Function, Register ) \\r
+ *QNCMmPci32Ptr( Segment, Bus, Device, Function, Register )\r
+\r
+#define QNCMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \\r
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) = \\r
+ (UINT32) ( \\r
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) | \\r
+ (UINT32)(OrData) \\r
+ )\r
+\r
+#define QNCMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \\r
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) = \\r
+ (UINT32) ( \\r
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) & \\r
+ (UINT32)(AndData) \\r
+ )\r
+\r
+#define QNCMmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) = \\r
+ (UINT32) ( \\r
+ ( QNCMmPci32( Segment, Bus, Device, Function, Register ) & \\r
+ (UINT32)(AndData) \\r
+ ) | \\r
+ (UINT32)(OrData) \\r
+ )\r
+//\r
+// UINT16\r
+//\r
+#define QNCMmPci16Ptr( Segment, Bus, Device, Function, Register ) \\r
+ ( (volatile UINT16 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )\r
+\r
+#define QNCMmPci16( Segment, Bus, Device, Function, Register ) \\r
+ *QNCMmPci16Ptr( Segment, Bus, Device, Function, Register )\r
+\r
+#define QNCMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \\r
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) = \\r
+ (UINT16) ( \\r
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) | \\r
+ (UINT16)(OrData) \\r
+ )\r
+\r
+#define QNCMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \\r
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) = \\r
+ (UINT16) ( \\r
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) & \\r
+ (UINT16)(AndData) \\r
+ )\r
+\r
+#define QNCMmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) = \\r
+ (UINT16) ( \\r
+ ( QNCMmPci16( Segment, Bus, Device, Function, Register ) & \\r
+ (UINT16)(AndData) \\r
+ ) | \\r
+ (UINT16)(OrData) \\r
+ )\r
+//\r
+// UINT8\r
+//\r
+#define QNCMmPci8Ptr( Segment, Bus, Device, Function, Register ) \\r
+ ( (volatile UINT8 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )\r
+\r
+#define QNCMmPci8( Segment, Bus, Device, Function, Register ) \\r
+ *QNCMmPci8Ptr( Segment, Bus, Device, Function, Register )\r
+\r
+#define QNCMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \\r
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) = \\r
+ (UINT8) ( \\r
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) | \\r
+ (UINT8)(OrData) \\r
+ )\r
+\r
+#define QNCMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \\r
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) = \\r
+ (UINT8) ( \\r
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) & \\r
+ (UINT8)(AndData) \\r
+ )\r
+\r
+#define QNCMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) = \\r
+ (UINT8) ( \\r
+ ( QNCMmPci8( Segment, Bus, Device, Function, Register ) & \\r
+ (UINT8)(AndData) \\r
+ ) | \\r
+ (UINT8)(OrData) \\r
+ )\r
+\r
+#endif\r
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