--- /dev/null
+/** @file\r
+QuarkNcSocId Register Definitions\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+Definitions beginning with "R_" are registers\r
+Definitions beginning with "B_" are bits within registers\r
+Definitions beginning with "V_" are meaningful values of bits within the registers\r
+Definitions beginning with "S_" are register sizes\r
+Definitions beginning with "N_" are the bit position\r
+\r
+**/\r
+\r
+#ifndef _QUARK_NC_SOC_ID_H_\r
+#define _QUARK_NC_SOC_ID_H_\r
+\r
+//\r
+// QNC GMCH Equates\r
+//\r
+\r
+//\r
+// DEVICE 0 (Memroy Controller Hub)\r
+//\r
+#define MC_BUS PCI_BUS_NUMBER_QNC\r
+#define MC_DEV 0x00\r
+#define MC_FUN 0x00\r
+\r
+#define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID\r
+#define QUARK_MC_DEVICE_ID 0x0958\r
+#define QUARK2_MC_DEVICE_ID 0x12C0\r
+#define QNC_MC_REV_ID_A0 0x00\r
+\r
+\r
+//\r
+// MCR - B0:D0:F0:RD0h (WO)- Message control register\r
+// [31:24] Message opcode - D0 read; E0 write;\r
+// [23:16] Message port\r
+// [15:8 ] Message target register address\r
+// [ 7:4 ] Message write byte enable : F is enable\r
+// [ 3:0 ] Reserved\r
+//\r
+#define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register\r
+// Always Set to 0xF0\r
+\r
+//\r
+//MDR - B0:D0:F0:RD4h (RW)- Message data register\r
+//\r
+#define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register\r
+\r
+//\r
+//MEA - B0:D0:F0:RD8h (RW)- Message extended address register\r
+//\r
+#define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Address Register\r
+\r
+#define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR\r
+#define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR\r
+#define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR\r
+\r
+//\r
+// Misc Useful Macros\r
+//\r
+\r
+#define LShift16(value) (value << 16)\r
+\r
+//\r
+// QNC Message OpCodes and Attributes\r
+//\r
+#define QUARK_OPCODE_READ 0x10 // Quark message bus "read" opcode\r
+#define QUARK_OPCODE_WRITE 0x11 // Quark message bus "write" opcode\r
+\r
+//\r
+// Alternative opcodes for the SCSS block\r
+//\r
+#define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus "read" opcode\r
+#define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus "write" opcode\r
+\r
+//\r
+// QNC Message OpCodes and Attributes for IO\r
+//\r
+#define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO read" opcode\r
+#define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO write" opcode\r
+\r
+\r
+#define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU Main binary shadow" opcode\r
+\r
+#define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management Unit "scrub resume" opcode\r
+#define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode\r
+\r
+//\r
+// QNC Message Ports and Registers\r
+//\r
+// Start of SB Port IDs\r
+#define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00\r
+#define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01\r
+#define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03\r
+#define QUARK_NC_RMU_SB_PORT_ID 0x04\r
+#define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05\r
+#define QUARK_SC_USB_AFE_SB_PORT_ID 0x14\r
+#define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16\r
+#define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31\r
+#define QUARK_SCSS_FUSE_SB_PORT_ID 0x33\r
+#define QUARK_ICLK_SB_PORT_ID 0x32\r
+#define QUARK_SCSS_CRU_SB_PORT_ID 0x34\r
+\r
+//\r
+// Quark Memory Arbiter Registers.\r
+//\r
+#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI Status encodings register.\r
+#define ASTATUS_PRI_CASUAL 0x0 // Serviced only if convenient\r
+#define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the DRAM is in Self-Refresh.\r
+#define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing.\r
+#define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing.\r
+#define ASTATUS1_RASISED_BP (10)\r
+#define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)\r
+#define ASTATUS0_RASISED_BP (8)\r
+#define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)\r
+#define ASTATUS1_DEFAULT_BP (2)\r
+#define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)\r
+#define ASTATUS0_DEFAULT_BP (0)\r
+#define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)\r
+\r
+//\r
+// Quark Memory Controller Registers.\r
+//\r
+#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register.\r
+#define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC.\r
+\r
+//\r
+// Quark Remote Management Unit Registers.\r
+//\r
+#define QNC_MSG_TMPM_REG_PMBA 0x70 // Power Management I/O Base Address\r
+\r
+#define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote Management Unit configuration register.\r
+#define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6)\r
+#define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5)\r
+\r
+#define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote Management Unit Options register 1.\r
+#define OPTIONS_1_DMA_DISABLE (BIT0)\r
+\r
+#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote Management Unit Watchdog control register.\r
+#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18)\r
+#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18\r
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)\r
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)\r
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)\r
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)\r
+\r
+#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register.\r
+#define TS_ENABLE (BIT15)\r
+#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register.\r
+#define TS_HOT_TRIP_CLEAR_THOLD_BP 24\r
+#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP)\r
+#define TS_CAT_TRIP_CLEAR_THOLD_BP 16\r
+#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP)\r
+#define TS_HOT_TRIP_SET_THOLD_BP 8\r
+#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP)\r
+#define TS_CAT_TRIP_SET_THOLD_BP 0\r
+#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP)\r
+\r
+#define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50\r
+#define SCRUB_CFG_INTERVAL_SHIFT 0x00\r
+#define SCRUB_CFG_INTERVAL_MASK 0xFF\r
+#define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08\r
+#define SCRUB_CFG_BLOCKSIZE_MASK 0x1F\r
+#define SCRUB_CFG_ACTIVE (BIT13)\r
+#define SCRUB_CFG_INVALID 0x00000FFF\r
+\r
+#define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76\r
+#define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77\r
+#define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C\r
+\r
+#define SCRUB_RESUME_MSG() ((UINT32)( \\r
+ (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \\r
+ (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \\r
+ 0xF0))\r
+\r
+#define SCRUB_PAUSE_MSG() ((UINT32)( \\r
+ (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \\r
+ (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \\r
+ 0xF0))\r
+\r
+//\r
+// Quark Memory Manager Registers\r
+//\r
+#define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82\r
+#define BLOCK_ENABLE_PG (1 << 28)\r
+#define BLOCK_DISABLE_PG (1 << 29)\r
+#define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19\r
+#define EnableIMRInt BIT31\r
+#define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C\r
+#define EnableSMMInt BIT31\r
+#define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20\r
+#define DRAM_NON_HOST_RQ_LIMIT_BP 0\r
+#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP)\r
+\r
+#define QUARK_NC_TOTAL_IMR_SET 0x8\r
+#define QUARK_NC_MEMORY_MANAGER_IMR0 0x40\r
+#define QUARK_NC_MEMORY_MANAGER_IMR1 0x44\r
+#define QUARK_NC_MEMORY_MANAGER_IMR2 0x48\r
+#define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C\r
+#define QUARK_NC_MEMORY_MANAGER_IMR4 0x50\r
+#define QUARK_NC_MEMORY_MANAGER_IMR5 0x54\r
+#define QUARK_NC_MEMORY_MANAGER_IMR6 0x58\r
+#define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C\r
+ #define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00\r
+ #define IMR_LOCK BIT31\r
+ #define IMR_EN BIT30\r
+ #define IMRL_MASK 0x00FFFFFC\r
+ #define IMRL_RESET 0x00000000\r
+ #define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01\r
+ #define IMRH_MASK 0x00FFFFFC\r
+ #define IMRH_RESET 0x00000000\r
+ #define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02\r
+ #define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03\r
+ #define IMRX_ALL_ACCESS 0xFFFFFFFF\r
+ #define CPU_SNOOP BIT30\r
+ #define RMU BIT29\r
+ #define CPU0_NON_SMM BIT0\r
+\r
+//\r
+// Quark Host Bridge Registers\r
+//\r
+#define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls\r
+#define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge)\r
+#define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control\r
+#define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN\r
+#define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN\r
+#define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN\r
+#define SMM_CTL_EN (BIT3) // SMM enable\r
+#define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN\r
+#define SMM_READ_OPEN (BIT1) // SMM Reads OPEN\r
+#define SMM_LOCKED (BIT0) // SMM Locked\r
+#define SMM_START_MASK 0x0000FFF0\r
+#define SMM_END_MASK 0xFFF00000\r
+#define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08\r
+#define HMBOUND_MASK 0x0FFFFF000\r
+#define HMBOUND_LOCK BIT0\r
+#define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A\r
+#define HLEGACY_SMI_PIN_VALUE BIT12\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54\r
+#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68\r
+#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69\r
+\r
+//\r
+// System On Chip Unit (SOCUnit) Registers.\r
+//\r
+#define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00\r
+#define B_STPDDRCFG_FORCE_RECOVERY BIT0\r
+#define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25\r
+#define B_ROM_FUSE_IN_SECURE_SKU BIT6\r
+\r
+#define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31\r
+#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3)\r
+#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3\r
+#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8)\r
+#define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8\r
+#define B_TSCGF1_CONFIG_IBGEN BIT17\r
+#define B_TSCGF1_CONFIG_IBGEN_BP 17\r
+#define B_TSCGF1_CONFIG_IBGCHOPEN BIT18\r
+#define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18\r
+#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14\r
+#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14\r
+\r
+#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32\r
+#define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF\r
+#define B_TSCGF2_CONFIG_IDSCONTROL_BP 0\r
+#define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000\r
+#define B_TSCGF2_CONFIG_IDSTIMING_BP 16\r
+\r
+#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33\r
+#define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000\r
+#define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24\r
+#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8)\r
+#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8\r
+#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF\r
+#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0\r
+\r
+#define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34\r
+#define B_TSCGF3_CONFIG_ITSRST BIT0\r
+#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11\r
+#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP)\r
+\r
+#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36\r
+#define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20\r
+#define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19\r
+#define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18\r
+#define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17\r
+#define SOCCLKEN_CONFIG_BB_RST_B BIT16\r
+\r
+#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36\r
+\r
+#define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51\r
+#define B_CFG_STICKY_RW_SMM_VIOLATION BIT0\r
+#define B_CFG_STICKY_RW_HMB_VIOLATION BIT1\r
+#define B_CFG_STICKY_RW_IMR_VIOLATION BIT2\r
+#define B_CFG_STICKY_RW_DECC_VIOLATION BIT3\r
+#define B_CFG_STICKY_RW_WARM_RST BIT4\r
+#define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9\r
+#define B_CFG_STICKY_RW_VIOLATION (B_CFG_STICKY_RW_SMM_VIOLATION | B_CFG_STICKY_RW_HMB_VIOLATION | B_CFG_STICKY_RW_IMR_VIOLATION | B_CFG_STICKY_RW_DECC_VIOLATION)\r
+#define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION | B_CFG_STICKY_RW_WARM_RST)\r
+\r
+//\r
+// iCLK Registers.\r
+//\r
+#define QUARK_ICLK_MUXTOP 0x0140\r
+#define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23)\r
+#define B_MUXTOP_FLEX2_BP 23\r
+#define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20)\r
+#define B_MUXTOP_FLEX1_BP 20\r
+\r
+#define QUARK_ICLK_SSC1 0x0314\r
+#define QUARK_ICLK_SSC2 0x0414\r
+#define QUARK_ICLK_SSC3 0x0514\r
+#define QUARK_ICLK_REF2_DBUFF0 0x2000\r
+\r
+//\r
+// PCIe AFE Unit Registers (QUARK_SC_PCIE_AFE_SB_PORT_ID).\r
+//\r
+#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080\r
+#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180\r
+#define OCFGPIMIXLOAD_1_0 BIT6\r
+#define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F\r
+\r
+//\r
+// QNC ICH Equates\r
+//\r
+#define V_INTEL_VENDOR_ID 0x8086\r
+\r
+#define PCI_BUS_NUMBER_QNC 0x00\r
+\r
+//\r
+// PCI to LPC Bridge Registers (D31:F0)\r
+//\r
+#define PCI_DEVICE_NUMBER_QNC_LPC 31\r
+#define PCI_FUNCTION_NUMBER_QNC_LPC 0\r
+\r
+#define R_QNC_LPC_VENDOR_ID 0x00\r
+#define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID\r
+#define R_QNC_LPC_DEVICE_ID 0x02\r
+#define QUARK_V_LPC_DEVICE_ID_0 0x095E\r
+#define R_QNC_LPC_REV_ID 0x08\r
+\r
+#define R_QNC_LPC_SMBUS_BASE 0x40 //~0x43\r
+#define B_QNC_LPC_SMBUS_BASE_EN (BIT31)\r
+#define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0 //[15:6]\r
+//\r
+// SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h)\r
+// Suggested Value for SMBA = 0x1040\r
+//\r
+#define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W\r
+#define B_QNC_SMBUS_START (BIT4) // Start/Stop\r
+#define V_QNC_SMBUS_HCTL_CMD_QUICK 0\r
+#define V_QNC_SMBUS_HCTL_CMD_BYTE 1\r
+#define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2\r
+#define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3\r
+#define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4\r
+#define V_QNC_SMBUS_HCTL_CMD_BLOCK 5\r
+\r
+#define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W\r
+#define B_QNC_SMBUS_BERR (BIT2) // BUS Error\r
+#define B_QNC_SMBUS_DERR (BIT1) // Device Error\r
+#define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status\r
+#define B_QNC_SMBUS_HSTS_ALL 0x07\r
+\r
+#define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W\r
+#define V_QNC_SMBUS_HCLK_100KHZ 0x0054\r
+\r
+#define R_QNC_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W\r
+#define V_QNC_SMBUS_RW_SEL_READ 1\r
+#define V_QNC_SMBUS_RW_SEL_WRITE 0\r
+\r
+#define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W\r
+#define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W\r
+#define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W\r
+#define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W [255:0] ~ 3Fh\r
+\r
+#define R_QNC_LPC_GBA_BASE 0x44\r
+#define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0\r
+//\r
+// GPIO register offsets from GBA - "GPIO" (D31:F0:R44h)\r
+// Suggested Value for GBA = 0x1080\r
+//\r
+#define R_QNC_GPIO_CGEN_CORE_WELL 0x00\r
+#define R_QNC_GPIO_CGIO_CORE_WELL 0x04\r
+#define R_QNC_GPIO_CGLVL_CORE_WELL 0x08\r
+#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable\r
+#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable\r
+#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable\r
+#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable\r
+#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status\r
+#define R_QNC_GPIO_RGEN_RESUME_WELL 0x20\r
+#define R_QNC_GPIO_RGIO_RESUME_WELL 0x24\r
+#define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28\r
+#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable\r
+#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable\r
+#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable\r
+#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable\r
+#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status\r
+#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable\r
+#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable\r
+\r
+#define R_QNC_LPC_PM1BLK 0x48\r
+#define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0\r
+//\r
+// ACPI register offsets from PM1BLK - "ACPI PM1 Block" (D31:F0:R48h)\r
+// Suggested Value for PM1BLK = 0x1000\r
+//\r
+#define R_QNC_PM1BLK_PM1S 0x00\r
+#define S_QNC_PM1BLK_PM1S 2\r
+#define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)\r
+#define B_QNC_PM1BLK_PM1S_WAKE (BIT15)\r
+#define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14)\r
+#define B_QNC_PM1BLK_PM1S_RTC (BIT10)\r
+#define B_QNC_PM1BLK_PM1S_GLOB (BIT5)\r
+#define B_QNC_PM1BLK_PM1S_TO (BIT0)\r
+#define N_QNC_PM1BLK_PM1S_RTC 10\r
+\r
+\r
+#define R_QNC_PM1BLK_PM1E 0x02\r
+#define S_QNC_PM1BLK_PM1E 2\r
+#define B_QNC_PM1BLK_PM1E_PWAKED (BIT14)\r
+#define B_QNC_PM1BLK_PM1E_RTC (BIT10)\r
+#define B_QNC_PM1BLK_PM1E_GLOB (BIT5)\r
+#define N_QNC_PM1BLK_PM1E_RTC 10\r
+\r
+#define R_QNC_PM1BLK_PM1C 0x04\r
+#define B_QNC_PM1BLK_PM1C_SLPEN (BIT13)\r
+#define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10)\r
+#define V_S0 0x00000000\r
+#define V_S3 0x00001400\r
+#define V_S4 0x00001800\r
+#define V_S5 0x00001C00\r
+#define B_QNC_PM1BLK_PM1C_SCIEN (BIT0)\r
+\r
+#define R_QNC_PM1BLK_PM1T 0x08\r
+\r
+#define R_QNC_LPC_GPE0BLK 0x4C\r
+#define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0\r
+// Suggested Value for GPE0BLK = 0x10C0\r
+//\r
+#define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status\r
+#define S_QNC_GPE0BLK_GPE0S 4\r
+#define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // used to clear the status reg\r
+#define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE\r
+#define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO\r
+#define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE\r
+#define N_QNC_GPE0BLK_GPE0S_THRM 12\r
+\r
+#define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable\r
+#define S_QNC_GPE0BLK_GPE0E 4\r
+#define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE\r
+#define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO\r
+#define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE\r
+#define N_QNC_GPE0BLK_GPE0E_THRM 12\r
+\r
+#define R_QNC_GPE0BLK_SMIE 0x10 // SMI_B Enable\r
+#define S_QNC_GPE0BLK_SMIE 4\r
+#define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F\r
+#define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM\r
+#define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep\r
+#define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer\r
+#define N_QNC_GPE0BLK_SMIE_GPIO 9\r
+#define N_QNC_GPE0BLK_SMIE_ESMI 8\r
+#define N_QNC_GPE0BLK_SMIE_APM 4\r
+#define N_QNC_GPE0BLK_SMIE_SPI 3\r
+#define N_QNC_GPE0BLK_SMIE_SLP 2\r
+#define N_QNC_GPE0BLK_SMIE_SWT 1\r
+\r
+#define R_QNC_GPE0BLK_SMIS 0x14 // SMI Status Register.\r
+#define S_QNC_GPE0BLK_SMIS 4\r
+#define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F\r
+#define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI\r
+#define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM\r
+#define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI\r
+#define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep\r
+#define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer\r
+#define B_QNC_GPE0BLK_SMIS_BIOS (BIT0) // BIOS\r
+#define N_QNC_GPE0BLK_SMIS_GPIO 9\r
+#define N_QNC_GPE0BLK_SMIS_APM 4\r
+#define N_QNC_GPE0BLK_SMIS_SPI 3\r
+#define N_QNC_GPE0BLK_SMIS_SLP 2\r
+#define N_QNC_GPE0BLK_SMIS_SWT 1\r
+\r
+#define R_QNC_GPE0BLK_PMCW 0x28 // Power Management Configuration Core Well\r
+#define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable\r
+\r
+#define R_QNC_GPE0BLK_PMSW 0x2C // Power Management Configuration Suspend/Resume Well\r
+#define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Initialization Sctrachpad\r
+\r
+#define R_QNC_LPC_ACTL 0x58\r
+#define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00\r
+\r
+//\r
+// Number of PIRQs supported. PIRQA~PIRQH\r
+//\r
+#define QNC_NUMBER_PIRQS 8\r
+#define R_QNC_LPC_PIRQA_ROUT 0x60\r
+#define R_QNC_LPC_PIRQB_ROUT 0x61\r
+#define R_QNC_LPC_PIRQC_ROUT 0x62\r
+#define R_QNC_LPC_PIRQD_ROUT 0x63\r
+#define R_QNC_LPC_PIRQE_ROUT 0x64\r
+#define R_QNC_LPC_PIRQF_ROUT 0x65\r
+#define R_QNC_LPC_PIRQG_ROUT 0x66\r
+#define R_QNC_LPC_PIRQH_ROUT 0x67\r
+\r
+//\r
+// Bit values are the same for R_TNC_LPC_PIRQA_ROUT to\r
+// R_TNC_LPC_PIRQH_ROUT\r
+#define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)\r
+\r
+#define R_QNC_LPC_WDTBA 0x84\r
+// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)------------BEGIN\r
+#define R_QNC_LPC_WDT_WDTCR 0x10\r
+#define R_QNC_LPC_WDT_WDTLR 0x18\r
+// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)--------------END\r
+\r
+#define R_QNC_LPC_FWH_BIOS_DEC 0xD4\r
+#define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31)\r
+#define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30)\r
+#define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29)\r
+#define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28)\r
+#define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27)\r
+#define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26)\r
+#define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25)\r
+#define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24)\r
+\r
+#define R_QNC_LPC_BIOS_CNTL 0xD8\r
+#define S_QNC_LPC_BIOS_CNTL 4\r
+#define B_QNC_LPC_BIOS_CNTL_PFE (BIT8)\r
+#define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5)\r
+#define B_QNC_LPC_BIOS_CNTL_BCD (BIT2)\r
+#define B_QNC_LPC_BIOS_CNTL_BLE (BIT1)\r
+#define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0)\r
+#define N_QNC_LPC_BIOS_CNTL_BLE 1\r
+#define N_QNC_LPC_BIOS_CNTL_BIOSWE 0\r
+\r
+#define R_QNC_LPC_RCBA 0xF0\r
+#define B_QNC_LPC_RCBA_MASK 0xFFFFC000\r
+#define B_QNC_LPC_RCBA_EN (BIT0)\r
+\r
+//---------------------------------------------------------------------------\r
+// Fixed IO Decode on QuarkNcSocId\r
+//\r
+// 20h(2B) 24h(2B) 28h(2B) 2Ch(2B) 30h(2B) 34h(2B) 38h(2B) 3Ch(2B) : R/W 8259 master\r
+// 40h(3B): R/W 8254\r
+// 43h(1B): W 8254\r
+// 50h(3B): R/W 8254\r
+// 53h(1B): W 8254\r
+// 61h(1B): R/W NMI Controller\r
+// 63h(1B): R/W NMI Controller - can be disabled\r
+// 65h(1B): R/W NMI Controller - can be disabled\r
+// 67h(1B): R/W NMI Controller - can be disabled\r
+// 70h(1B): W NMI & RTC\r
+// 71h(1B): R/W RTC\r
+// 72h(1B): R RTC; W NMI&RTC\r
+// 73h(1B): R/W RTC\r
+// 74h(1B): R RTC; W NMI&RTC\r
+// 75h(1B): R/W RTC\r
+// 76h(1B): R RTC; W NMI&RTC\r
+// 77h(1B): R/W RTC\r
+// 84h(3B): R/W Internal/LPC\r
+// 88h(1B): R/W Internal/LPC\r
+// 8Ch(3B): R/W Internal/LPC\r
+// A0h(2B) A4h(2B) A8h(2B) ACh(2B) B0h(2B) B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave\r
+// B2h(1B) B3h(1B): R/W Power management\r
+// 3B0h-3BBh: R/W VGA\r
+// 3C0h-3DFh: R/W VGA\r
+// CF8h(4B): R/W Internal\r
+// CF9h(1B): R/W LPC\r
+// CFCh(4B): R/W Internal\r
+//---------------------------------------------------------------------------\r
+\r
+#define R_APM_CNT 0xB2\r
+\r
+//\r
+// Reset Generator I/O Port\r
+//\r
+#define RST_CNT 0xCF9\r
+#define B_RST_CNT_COLD_RST (BIT3) // Cold reset\r
+#define B_RST_CNT_WARM_RST (BIT1) // Warm reset\r
+\r
+//\r
+// Processor interface registers (NMI)\r
+//\r
+\r
+#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20\r
+#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21\r
+#define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0\r
+\r
+//\r
+// Pci Express Root Ports (D23:F0/F1)\r
+//\r
+#define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23\r
+#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0\r
+#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1\r
+\r
+#define MAX_PCI_EXPRESS_ROOT_PORTS 2\r
+\r
+#define R_QNC_PCIE_BNUM 0x18\r
+#define R_QNC_PCIE_CAP_PTR 0x34\r
+\r
+#define PCIE_CAPID 0x10 //PCIE Capability ID\r
+#define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID\r
+#define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability reg offset\r
+#define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability reg offset\r
+#define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset\r
+#define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset\r
+#define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability reg offset\r
+\r
+#define R_QNC_PCIE_XCAP 0x42 //~ 43h\r
+#define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented\r
+#define R_QNC_PCIE_DCAP 0x44 //~ 47h\r
+#define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency\r
+#define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit latency\r
+#define R_QNC_PCIE_DCTL 0x48 //~ 49h\r
+#define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable\r
+#define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable\r
+#define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable\r
+#define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error Reporting Enable\r
+#define R_QNC_PCIE_LCAP 0x4C //~ 4Fh\r
+#define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported\r
+#define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask\r
+#define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask\r
+#define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10) //Active state link PM support mask\r
+#define V_QNC_PCIE_LCAP_APMS_OFFSET 10 //Active state link PM support mask\r
+#define R_QNC_PCIE_LCTL 0x50 //~ 51h\r
+#define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock configuration\r
+#define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link\r
+#define R_QNC_PCIE_LSTS 0x52 //~ 53h\r
+#define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration\r
+#define B_QNC_PCIE_LSTS_LT (BIT11) //Link training\r
+#define R_QNC_PCIE_SLCAP 0x54 //~ 57h\r
+#define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F\r
+#define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value [14:7]\r
+#define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit value offset is 7 [14:7]\r
+#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset is 19 [31:19]\r
+#define R_QNC_PCIE_SLCTL 0x58 //~ 59h\r
+#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug interrupt enable\r
+#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable\r
+#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attention Button Pressed Enable\r
+#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh\r
+#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State = 1b : has device connected\r
+#define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS state has changed\r
+#define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attention Button Pressed\r
+#define R_QNC_PCIE_RCTL 0x5C //~ 5Dh\r
+#define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable\r
+#define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Error Enable\r
+#define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fatal Error Enable\r
+#define B_QNC_PCIE_RCTL_SCE (BIT0) //Root PCI-E System Error on Correctable Error Enable\r
+#define R_QNC_PCIE_SVID 0x94 //~ 97h\r
+#define R_QNC_PCIE_CCFG 0xD0 //~ D3h\r
+#define B_QNC_PCIE_CCFG_UPSD (BIT24) // Upstream Posted Split Disable\r
+#define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size\r
+#define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size\r
+#define R_QNC_PCIE_MPC2 0xD4 //~ D7h\r
+#define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Transmit Mode\r
+#define R_QNC_PCIE_MPC 0xD8 //~ DBh\r
+#define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable\r
+#define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable\r
+\r
+#define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable\r
+#define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable\r
+#define R_QNC_PCIE_IOSFSBCTL 0xF6\r
+#define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0) // IOSF Sideband ISM Idle Counter.\r
+#define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0) // Never transition to IDLE.\r
+\r
+#define V_PCIE_MAX_TRY_TIMES 200\r
+\r
+//\r
+// Misc PCI register offsets and sizes\r
+//\r
+#define R_EFI_PCI_SVID 0x2C\r
+\r
+//\r
+// IO_APIC\r
+//\r
+#define IOAPIC_BASE 0xFEC00000\r
+#define IOAPIC_SIZE 0x1000\r
+\r
+//\r
+// Chipset configuration registers RCBA - "Root Complex Base Address" (D31:F0:RF0h)\r
+// Suggested Value for RCBA = 0xFED1C000\r
+//\r
+\r
+#define R_QNC_RCRB_SPIBASE 0x3020 // SPI (Serial Peripheral Interface) in RCRB\r
+#define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status\r
+#define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown\r
+#define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status\r
+#define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status\r
+#define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress\r
+\r
+#define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control\r
+#define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable\r
+#define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,32,40,48,56,64)\r
+#define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer\r
+#define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer\r
+#define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence\r
+#define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go\r
+\r
+#define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address\r
+#define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask\r
+#define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08) // SPI Data 0\r
+#define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54) // Prefix Opcode Configuration\r
+#define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56) // Opcode Type Configuration\r
+#define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0\r
+#define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0)\r
+#define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1)\r
+#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1)\r
+#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) // Opcode Menu Configuration //R_OPMENU\r
+\r
+#define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60) // Protected BIOS Range 0.\r
+#define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64) // Protected BIOS Range 1.\r
+#define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68) // Protected BIOS Range 2.\r
+#define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers.\r
+\r
+#define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route\r
+#define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route\r
+#define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route\r
+#define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route\r
+\r
+#endif\r
projects / mirror_edk2.git / blobdiff