QuarkSocPkg: Add new package for Quark SoC X1000

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / MemoryInit / Pei / memory_options.h

diff --git a/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/memory_options.h b/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/memory_options.h
new file mode 100644 (file)
index 0000000..8452b98
--- /dev/null
+++ b/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/memory_options.h
@@ -0,0 +1,83 @@
+/** @file\r
+Common definitions and compilation switches for MRC\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#ifndef __MEMORY_OPTIONS_H\r
+#define __MEMORY_OPTIONS_H\r
+\r
+#include "core_types.h"\r
+\r
+// MRC COMPILE TIME SWITCHES:\r
+// ==========================\r
+\r
+\r
+\r
+//#define MRC_SV              // enable some validation opitons\r
+\r
+#if defined (SIM) || defined(EMU)\r
+#define QUICKSIM              // reduce execution time using shorter rd/wr sequences\r
+#endif\r
+\r
+#define CLT                   // required for Quark project\r
+\r
+\r
+\r
+//#define BACKUP_RCVN           // enable STATIC timing settings for RCVN (BACKUP_MODE)\r
+//#define BACKUP_WDQS           // enable STATIC timing settings for WDQS (BACKUP_MODE)\r
+//#define BACKUP_RDQS           // enable STATIC timing settings for RDQS (BACKUP_MODE)\r
+//#define BACKUP_WDQ            // enable STATIC timing settings for WDQ (BACKUP_MODE)\r
+\r
+\r
+\r
+//#define BACKUP_COMPS          // enable *COMP overrides (BACKUP_MODE)\r
+//#define RX_EYE_CHECK          // enable the RD_TRAIN eye check\r
+#define HMC_TEST              // enable Host to Memory Clock Alignment\r
+#define R2R_SHARING           // enable multi-rank support via rank2rank sharing\r
+\r
+#define FORCE_16BIT_DDRIO     // disable signals not used in 16bit mode of DDRIO\r
+\r
+\r
+\r
+//\r
+// Debug support\r
+//\r
+\r
+#ifdef NDEBUG\r
+#define DPF        if(0) dpf\r
+#else\r
+#define DPF        dpf\r
+#endif\r
+\r
+void dpf( uint32_t mask, char_t *bla, ...);\r
+\r
+\r
+uint8_t mgetc(void);\r
+uint8_t mgetch(void);\r
+\r
+\r
+// Debug print type\r
+#define D_ERROR      0x0001\r
+#define D_INFO       0x0002\r
+#define D_REGRD      0x0004\r
+#define D_REGWR      0x0008\r
+#define D_FCALL      0x0010\r
+#define D_TRN        0x0020\r
+#define D_TIME       0x0040\r
+\r
+#define ENTERFN()     DPF(D_FCALL, "<%s>\n", __FUNCTION__)\r
+#define LEAVEFN()     DPF(D_FCALL, "</%s>\n", __FUNCTION__)\r
+#define REPORTFN()    DPF(D_FCALL, "<%s/>\n", __FUNCTION__)\r
+\r
+extern uint32_t DpfPrintMask;\r
+\r
+#endif\r