--- /dev/null
+/** @file\r
+Header file for the PCH SPI Common Driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#ifndef _SPI_COMMON_H_\r
+#define _SPI_COMMON_H_\r
+\r
+#include "Protocol/Spi.h"\r
+#include <Library/PciLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/IntelQNCLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+#include <Uefi/UefiBaseType.h>\r
+\r
+//\r
+// Maximum time allowed while waiting the SPI cycle to complete\r
+// Wait Time = 6 seconds = 6000000 microseconds\r
+// Wait Period = 10 microseconds\r
+//\r
+#define WAIT_TIME 6000000\r
+#define WAIT_PERIOD 10\r
+//\r
+// PCH Required SPI Commands -------- COMMAND SET I ------------\r
+// SPI flash device must support in order to be compatible with PCH\r
+//\r
+#define PCH_SPI_COMMAND_PROGRAM_BYTE 0x02\r
+#define PCH_SPI_COMMAND_READ_DATA 0x03\r
+#define PCH_SPI_COMMAND_WRITE_DISABLE 0x04\r
+#define PCH_SPI_COMMAND_READ_STATUS 0x05\r
+#define PCH_SPI_COMMAND_WRITE_ENABLE 0x06\r
+#define PCH_SPI_COMMAND_FAST_READ 0x0B\r
+#define PCH_SPI_COMMAND_READ_ID 0x9F\r
+#define PCH_SPI_COMMAND_DUAL_FAST_READ 0x3B // Dual Output Fast Read\r
+\r
+//\r
+// Need to support at least one of the following two kinds of size of sector for erasing\r
+//\r
+#define PCH_SPI_COMMAND_4KB_ERASE 0x20\r
+#define PCH_SPI_COMMAND_64KB_ERASE 0xD8\r
+//\r
+// Recommended SPI Commands -------- COMMAND SET II ------------\r
+// SPI flash device best to support\r
+//\r
+#define PCH_SPI_COMMAND_WRITE_STATUS 0x01\r
+#define PCH_SPI_COMMAND_FULL_CHIP_ERASE 0xC7\r
+\r
+//\r
+// Private data structure definitions for the driver\r
+//\r
+#define PCH_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')\r
+\r
+typedef struct {\r
+ UINTN Signature;\r
+ EFI_HANDLE Handle;\r
+ EFI_SPI_PROTOCOL SpiProtocol;\r
+ SPI_INIT_TABLE SpiInitTable;\r
+ UINTN PchRootComplexBar;\r
+ BOOLEAN InitDone; // Set to TRUE on SpiProtocolInit SUCCESS.\r
+ SPI_INIT_INFO InitInfo;\r
+} SPI_INSTANCE;\r
+\r
+#define SPI_INSTANCE_FROM_SPIPROTOCOL(a) CR (a, SPI_INSTANCE, SpiProtocol, PCH_SPI_PRIVATE_DATA_SIGNATURE)\r
+\r
+//\r
+// Function prototypes used by the SPI protocol.\r
+//\r
+EFI_STATUS\r
+SpiProtocolConstructor (\r
+ SPI_INSTANCE *SpiInstance\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Initialize an SPI protocol instance.\r
+ The function will assert in debug if PCH RCBA has not been initialized\r
+\r
+Arguments:\r
+\r
+ SpiInstance - Pointer to SpiInstance to initialize\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS The protocol instance was properly initialized\r
+ EFI_UNSUPPORTED The PCH is not supported by this module\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SpiProtocolInit (\r
+ IN EFI_SPI_PROTOCOL *This,\r
+ IN SPI_INIT_TABLE *InitTable\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Initialize the host controller to execute SPI command.\r
+\r
+Arguments:\r
+\r
+ This Pointer to the EFI_SPI_PROTOCOL instance.\r
+ InitTable Initialization data to be programmed into the SPI host controller.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS Initialization completed.\r
+ EFI_ACCESS_DENIED The SPI static configuration interface has been locked-down.\r
+ EFI_INVALID_PARAMETER Bad input parameters.\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SpiProtocolLock (\r
+ IN EFI_SPI_PROTOCOL *This\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Lock the SPI Static Configuration Interface.\r
+ Once locked, the interface can not be changed and can only be clear by system reset.\r
+\r
+Arguments:\r
+\r
+ This Pointer to the EFI_SPI_PROTOCOL instance.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS Lock operation succeed.\r
+ EFI_DEVICE_ERROR Device error, operation failed.\r
+ EFI_ACCESS_DENIED The interface has already been locked.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SpiProtocolExecute (\r
+ IN EFI_SPI_PROTOCOL *This,\r
+ IN UINT8 OpcodeIndex,\r
+ IN UINT8 PrefixOpcodeIndex,\r
+ IN BOOLEAN DataCycle,\r
+ IN BOOLEAN Atomic,\r
+ IN BOOLEAN ShiftOut,\r
+ IN UINTN Address,\r
+ IN UINT32 DataByteCount,\r
+ IN OUT UINT8 *Buffer,\r
+ IN SPI_REGION_TYPE SpiRegionType\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Execute SPI commands from the host controller.\r
+\r
+Arguments:\r
+\r
+ This Pointer to the EFI_SPI_PROTOCOL instance.\r
+ OpcodeIndex Index of the command in the OpCode Menu.\r
+ PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
+ DataCycle TRUE if the SPI cycle contains data\r
+ Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
+ ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
+ Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
+ Region, this value specifies the offset from the Region Base; for BIOS Region,\r
+ this value specifies the offset from the start of the BIOS Image. In Non\r
+ Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
+ Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
+ Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
+ supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
+ the flash (in Non Descriptor Mode)\r
+ DataByteCount Number of bytes in the data portion of the SPI cycle.\r
+ Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
+ SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
+ EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
+ Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
+ and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
+ to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS Command succeed.\r
+ EFI_INVALID_PARAMETER The parameters specified are not valid.\r
+ EFI_UNSUPPORTED Command not supported.\r
+ EFI_DEVICE_ERROR Device error, command aborts abnormally.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+SendSpiCmd (\r
+ IN EFI_SPI_PROTOCOL *This,\r
+ IN UINT8 OpcodeIndex,\r
+ IN UINT8 PrefixOpcodeIndex,\r
+ IN BOOLEAN DataCycle,\r
+ IN BOOLEAN Atomic,\r
+ IN BOOLEAN ShiftOut,\r
+ IN UINTN Address,\r
+ IN UINT32 DataByteCount,\r
+ IN OUT UINT8 *Buffer,\r
+ IN SPI_REGION_TYPE SpiRegionType\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ This function sends the programmed SPI command to the slave device.\r
+\r
+Arguments:\r
+\r
+ OpcodeIndex Index of the command in the OpCode Menu.\r
+ PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
+ DataCycle TRUE if the SPI cycle contains data\r
+ Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
+ ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
+ Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
+ Region, this value specifies the offset from the Region Base; for BIOS Region,\r
+ this value specifies the offset from the start of the BIOS Image. In Non\r
+ Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
+ Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
+ Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
+ supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
+ the flash (in Non Descriptor Mode)\r
+ DataByteCount Number of bytes in the data portion of the SPI cycle. This function may break the\r
+ data transfer into multiple operations. This function ensures each operation does\r
+ not cross 256 byte flash address boundary.\r
+ *NOTE: if there is some SPI chip that has a stricter address boundary requirement\r
+ (e.g., its write page size is < 256 byte), then the caller cannot rely on this\r
+ function to cut the data transfer at proper address boundaries, and it's the\r
+ caller's reponsibility to pass in a properly cut DataByteCount parameter.\r
+ Buffer Data received or sent during the SPI cycle.\r
+ SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
+ EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
+ Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
+ and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
+ to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS SPI command completes successfully.\r
+ EFI_DEVICE_ERROR Device error, the command aborts abnormally.\r
+ EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode\r
+ EFI_INVALID_PARAMETER The parameters specified are not valid.\r
+\r
+--*/\r
+;\r
+\r
+BOOLEAN\r
+WaitForSpiCycleComplete (\r
+ IN EFI_SPI_PROTOCOL *This,\r
+ IN BOOLEAN ErrorCheck\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Wait execution cycle to complete on the SPI interface. Check both Hardware\r
+ and Software Sequencing status registers\r
+\r
+Arguments:\r
+\r
+ This - The SPI protocol instance\r
+ UseSoftwareSequence - TRUE if this is a Hardware Sequencing operation\r
+ ErrorCheck - TRUE if the SpiCycle needs to do the error check\r
+\r
+Returns:\r
+\r
+ TRUE SPI cycle completed on the interface.\r
+ FALSE Time out while waiting the SPI cycle to complete.\r
+ It's not safe to program the next command on the SPI interface.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SpiProtocolInfo (\r
+ IN EFI_SPI_PROTOCOL *This,\r
+ OUT SPI_INIT_INFO **InitInfoPtr\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Return info about SPI host controller, to help callers usage of Execute\r
+ service.\r
+\r
+ If 0xff is returned as an opcode index in init info struct\r
+ then device does not support the operation.\r
+\r
+Arguments:\r
+\r
+ This Pointer to the EFI_SPI_PROTOCOL instance.\r
+ InitInfoPtr Pointer to init info written to this memory location.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS Information returned.\r
+ EFI_INVALID_PARAMETER Invalid parameter.\r
+ EFI_NOT_READY Required resources not setup.\r
+ Others Unexpected error happened.\r
+\r
+--*/\r
+;\r
+\r
+#endif\r
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