--- /dev/null
+/** @file\r
+Header file for QuarkSCSocId Ioh.\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+#ifndef _IOH_H_\r
+#define _IOH_H_\r
+\r
+#ifndef BIT0\r
+#define BIT0 0x01\r
+#define BIT1 0x02\r
+#define BIT2 0x04\r
+#define BIT3 0x08\r
+#define BIT4 0x10\r
+#define BIT5 0x20\r
+#define BIT6 0x40\r
+#define BIT7 0x80\r
+#define BIT8 0x100\r
+#define BIT9 0x200\r
+#define BIT00 0x00000001\r
+#define BIT01 0x00000002\r
+#define BIT02 0x00000004\r
+#define BIT03 0x00000008\r
+#define BIT04 0x00000010\r
+#define BIT05 0x00000020\r
+#define BIT06 0x00000040\r
+#define BIT07 0x00000080\r
+#define BIT08 0x00000100\r
+#define BIT09 0x00000200\r
+#define BIT10 0x00000400\r
+#define BIT11 0x00000800\r
+#define BIT12 0x00001000\r
+#define BIT13 0x00002000\r
+#define BIT14 0x00004000\r
+#define BIT15 0x00008000\r
+#define BIT16 0x00010000\r
+#define BIT17 0x00020000\r
+#define BIT18 0x00040000\r
+#define BIT19 0x00080000\r
+#define BIT20 0x00100000\r
+#define BIT21 0x00200000\r
+#define BIT22 0x00400000\r
+#define BIT23 0x00800000\r
+#define BIT24 0x01000000\r
+#define BIT25 0x02000000\r
+#define BIT26 0x04000000\r
+#define BIT27 0x08000000\r
+#define BIT28 0x10000000\r
+#define BIT29 0x20000000\r
+#define BIT30 0x40000000\r
+#define BIT31 0x80000000\r
+#endif\r
+\r
+#define IOH_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r
+ ((UINT32) ( (((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \\r
+ (((UINTN)func) << 8) + ((UINTN)reg) ))& 0x00000000ffffffff\r
+\r
+//----------------------------------------------------------------------------\r
+\r
+#define INTEL_VENDOR_ID 0x8086 // Intel Vendor ID\r
+\r
+//----------------------------------------------------------------------------\r
+// Pci Configuration Map Register Offsets\r
+//----------------------------------------------------------------------------\r
+#define PCI_REG_VID 0x00 // Vendor ID Register\r
+#define PCI_REG_DID 0x02 // Device ID Register\r
+#define PCI_REG_PCICMD 0x04 // PCI Command Register\r
+#define PCI_REG_PCISTS 0x06 // PCI Status Register\r
+#define PCI_REG_RID 0x08 // PCI Revision ID Register\r
+#define PCI_REG_PI 0x09 // Programming Interface\r
+#define PCI_REG_SCC 0x0a // Sub Class Code Register\r
+#define PCI_REG_BCC 0x0b // Base Class Code Register\r
+#define PCI_REG_PMLT 0x0d // Primary Master Latnecy Timer\r
+#define PCI_REG_HDR 0x0e // Header Type Register\r
+#define PCI_REG_PBUS 0x18 // Primary Bus Number Register\r
+#define PCI_REG_SBUS 0x19 // Secondary Bus Number Register\r
+#define PCI_REG_SUBUS 0x1a // Subordinate Bus Number Register\r
+#define PCI_REG_SMLT 0x1b // Secondary Master Latnecy Timer\r
+#define PCI_REG_IOBASE 0x1c // I/O base Register\r
+#define PCI_REG_IOLIMIT 0x1d // I/O Limit Register\r
+#define PCI_REG_SECSTATUS 0x1e // Secondary Status Register\r
+#define PCI_REG_MEMBASE 0x20 // Memory Base Register\r
+#define PCI_REG_MEMLIMIT 0x22 // Memory Limit Register\r
+#define PCI_REG_PRE_MEMBASE 0x24 // Prefretchable memory Base register\r
+#define PCI_REG_PRE_MEMLIMIT 0x26 // Prefretchable memory Limit register\r
+#define PCI_REG_SVID0 0x2c // Subsystem Vendor ID low byte\r
+#define PCI_REG_SVID1 0x2d // Subsystem Vendor ID high byte\r
+#define PCI_REG_SID0 0x2e // Subsystem ID low byte\r
+#define PCI_REG_SID1 0x2f // Subsystem ID high byte\r
+#define PCI_REG_IOBASE_U 0x30 // I/O base Upper Register\r
+#define PCI_REG_IOLIMIT_U 0x32 // I/O Limit Upper Register\r
+#define PCI_REG_INTLINE 0x3c // Interrupt Line Register\r
+#define PCI_REG_BRIDGE_CNTL 0x3e // Bridge Control Register\r
+\r
+//---------------------------------------------------------------------------\r
+// QuarkSCSocId Packet Hub definitions\r
+//---------------------------------------------------------------------------\r
+\r
+#define PCIE_BRIDGE_VID_DID 0x88008086\r
+\r
+//---------------------------------------------------------------------------\r
+// Quark South Cluster definitions.\r
+//---------------------------------------------------------------------------\r
+\r
+#define IOH_BUS 0\r
+#define IOH_PCI_IOSF2AHB_0_DEV_NUM 0x14\r
+#define IOH_PCI_IOSF2AHB_0_MAX_FUNCS 7\r
+#define IOH_PCI_IOSF2AHB_1_DEV_NUM 0x15\r
+#define IOH_PCI_IOSF2AHB_1_MAX_FUNCS 3\r
+\r
+//---------------------------------------------------------------------------\r
+// Quark South Cluster USB definitions.\r
+//---------------------------------------------------------------------------\r
+\r
+#define IOH_USB_BUS_NUMBER IOH_BUS\r
+#define IOH_USB_CONTROLLER_MMIO_RANGE 0x1000\r
+#define IOH_MAX_OHCI_USB_CONTROLLERS 1\r
+#define IOH_MAX_EHCI_USB_CONTROLLERS 1\r
+#define IOH_MAX_USBDEVICE_USB_CONTROLLERS 1\r
+\r
+#define R_IOH_USB_VENDOR_ID 0x00\r
+#define V_IOH_USB_VENDOR_ID INTEL_VENDOR_ID\r
+#define R_IOH_USB_DEVICE_ID 0x02\r
+#define R_IOH_USB_COMMAND 0x04\r
+#define B_IOH_USB_COMMAND_BME BIT2\r
+#define B_IOH_USB_COMMAND_MSE BIT1\r
+#define B_IOH_USB_COMMAND_ISE BIT0\r
+#define R_IOH_USB_MEMBAR 0x10\r
+#define B_IOH_USB_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].\r
+#define R_IOH_USB_OHCI_HCCABAR 0x18\r
+\r
+//---------------------------------------------------------------------------\r
+// Quark South Cluster OHCI definitions\r
+//---------------------------------------------------------------------------\r
+#define IOH_USB_OHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r
+#define IOH_OHCI_FUNCTION_NUMBER 0x04\r
+\r
+//---------------------------------------------------------------------------\r
+// Quark South Cluster EHCI definitions\r
+//---------------------------------------------------------------------------\r
+#define IOH_USB_EHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r
+#define IOH_EHCI_FUNCTION_NUMBER 0x03\r
+\r
+//\r
+// EHCI memory mapped registers offset from memory BAR0.\r
+//\r
+#define R_IOH_EHCI_CAPLENGTH 0x00\r
+#define R_IOH_EHCI_INSNREG01 0x94\r
+#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP (16)\r
+#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)\r
+#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP (0)\r
+#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)\r
+\r
+//\r
+// EHCI memory mapped registers offset from memory BAR0 + Cap length value.\r
+//\r
+#define R_IOH_EHCI_CONFIGFLAGS 0x40\r
+\r
+//---------------------------------------------------------------------------\r
+// Quark South Cluster USB Device definitions\r
+//---------------------------------------------------------------------------\r
+#define IOH_USBDEVICE_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r
+#define IOH_USBDEVICE_FUNCTION_NUMBER 0x02\r
+\r
+//\r
+// USB Device memory mapped registers offset from memory BAR0.\r
+//\r
+#define R_IOH_USBDEVICE_D_INTR_UDC_REG 0x40c\r
+#define R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG 0x410\r
+#define B_IOH_USBDEVICE_D_INTR_MSK_UDC_REG_MASK1_MASK 0xff\r
+#define R_IOH_USBDEVICE_EP_INTR_UDC_REG 0x414\r
+#define R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG 0x418\r
+#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK 0x000f0000\r
+#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK 0x0000000f\r
+\r
+//---------------------------------------------------------------------------\r
+// Quark South Cluster 10/100 Mbps Ethernet Device definitions.\r
+//---------------------------------------------------------------------------\r
+#define IOH_MAC0_BUS_NUMBER IOH_BUS\r
+#define IOH_MAC0_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r
+#define IOH_MAC0_FUNCTION_NUMBER 0x06\r
+#define IOH_MAC1_BUS_NUMBER IOH_BUS\r
+#define IOH_MAC1_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r
+#define IOH_MAC1_FUNCTION_NUMBER 0x07\r
+\r
+//\r
+// MAC Device PCI config registers.\r
+//\r
+#define R_IOH_MAC_DEVICE_ID 0x02\r
+#define V_IOH_MAC_VENDOR_ID INTEL_VENDOR_ID\r
+#define R_IOH_MAC_DEVICE_ID 0x02\r
+#define V_IOH_MAC_DEVICE_ID 0x0937\r
+#define R_IOH_MAC_COMMAND 0x04\r
+#define B_IOH_MAC_COMMAND_BME BIT2\r
+#define B_IOH_MAC_COMMAND_MSE BIT1\r
+#define B_IOH_MAC_COMMAND_ISE BIT0\r
+#define R_IOH_MAC_MEMBAR 0x10\r
+#define B_IOH_MAC_MEMBAR_ADDRESS_MASK 0xFFFFF000\r
+\r
+//\r
+// LAN Device memory mapped registers offset from memory BAR0.\r
+//\r
+#define R_IOH_MAC_GMAC_REG_8 0x20\r
+#define B_IOH_MAC_USERVER_MASK 0x0000FF00\r
+#define B_IOH_MAC_SNPSVER_MASK 0x000000FF\r
+#define R_IOH_MAC_GMAC_REG_16 0x40\r
+#define B_IOH_MAC_ADDRHI_MASK 0x0000FFFF\r
+#define B_IOH_MAC_AE BIT31\r
+#define R_IOH_MAC_GMAC_REG_17 0x44\r
+#define B_IOH_MAC_ADDRLO_MASK 0xFFFFFFFF\r
+\r
+//---------------------------------------------------------------------------\r
+// Quark I2C / GPIO definitions\r
+//---------------------------------------------------------------------------\r
+\r
+#define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID\r
+#define V_IOH_I2C_GPIO_DEVICE_ID 0x0934\r
+\r
+#define R_IOH_I2C_MEMBAR 0x10\r
+#define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12].\r
+\r
+#define GPIO_SWPORTA_DR 0x00\r
+#define GPIO_SWPORTA_DDR 0x04\r
+#define GPIO_INTEN 0x30\r
+#define GPIO_INTMASK 0x34\r
+#define GPIO_INTTYPE_LEVEL 0x38\r
+#define GPIO_INT_POLARITY 0x3C\r
+#define GPIO_INTSTATUS 0x40\r
+#define GPIO_RAW_INTSTATUS 0x44\r
+#define GPIO_DEBOUNCE 0x48\r
+#define GPIO_PORTA_EOI 0x4C\r
+#define GPIO_EXT_PORTA 0x50\r
+#define GPIO_EXT_PORTB 0x54\r
+#define GPIO_LS_SYNC 0x60\r
+#define GPIO_CONFIG_REG2 0x70\r
+#define GPIO_CONFIG_REG1 0x74\r
+\r
+//---------------------------------------------------------------------------\r
+// Quark South Cluster UART definitions.\r
+//---------------------------------------------------------------------------\r
+\r
+#define R_IOH_UART_MEMBAR 0x10\r
+#define B_IOH_UART_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].\r
+\r
+#endif\r
projects / mirror_edk2.git / blobdiff