/** @file\r
TIS (TPM Interface Specification) functions used by dTPM2.0 library.\r
- \r
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php\r
\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
+(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Library/Tpm2DeviceLib.h>\r
#include <Library/PcdLib.h>\r
\r
-//\r
-// Set structure alignment to 1-byte\r
-//\r
-#pragma pack (1)\r
-\r
-//\r
-// Register set map as specified in TIS specification Chapter 10\r
-//\r
-typedef struct {\r
- ///\r
- /// Used to gain ownership for this particular port.\r
- ///\r
- UINT8 Access; // 0\r
- UINT8 Reserved1[7]; // 1\r
- ///\r
- /// Controls interrupts.\r
- ///\r
- UINT32 IntEnable; // 8\r
- ///\r
- /// SIRQ vector to be used by the TPM.\r
- ///\r
- UINT8 IntVector; // 0ch\r
- UINT8 Reserved2[3]; // 0dh\r
- ///\r
- /// What caused interrupt.\r
- ///\r
- UINT32 IntSts; // 10h\r
- ///\r
- /// Shows which interrupts are supported by that particular TPM.\r
- ///\r
- UINT32 IntfCapability; // 14h\r
- ///\r
- /// Status Register. Provides status of the TPM.\r
- ///\r
- UINT8 Status; // 18h\r
- ///\r
- /// Number of consecutive writes that can be done to the TPM.\r
- ///\r
- UINT16 BurstCount; // 19h\r
- ///\r
- /// TPM2 support CANCEL at BIT[24] of STATUS register (WO)\r
- ///\r
- UINT8 StatusEx; // 1Bh\r
- UINT8 Reserved3[8];\r
- ///\r
- /// Read or write FIFO, depending on transaction.\r
- ///\r
- UINT32 DataFifo; // 24h\r
- UINT8 Reserved4[0xed8]; // 28h\r
- ///\r
- /// Vendor ID\r
- ///\r
- UINT16 Vid; // 0f00h\r
- ///\r
- /// Device ID\r
- ///\r
- UINT16 Did; // 0f02h\r
- ///\r
- /// Revision ID\r
- ///\r
- UINT8 Rid; // 0f04h\r
- ///\r
- /// TCG defined configuration registers.\r
- ///\r
- UINT8 TcgDefined[0x7b]; // 0f05h\r
- ///\r
- /// Alias to I/O legacy space.\r
- ///\r
- UINT32 LegacyAddress1; // 0f80h\r
- ///\r
- /// Additional 8 bits for I/O legacy space extension.\r
- ///\r
- UINT32 LegacyAddress1Ex; // 0f84h\r
- ///\r
- /// Alias to second I/O legacy space.\r
- ///\r
- UINT32 LegacyAddress2; // 0f88h\r
- ///\r
- /// Additional 8 bits for second I/O legacy space extension.\r
- ///\r
- UINT32 LegacyAddress2Ex; // 0f8ch\r
- ///\r
- /// Vendor-defined configuration registers.\r
- ///\r
- UINT8 VendorDefined[0x70];// 0f90h\r
-} TIS_PC_REGISTERS;\r
-\r
-//\r
-// Restore original structure alignment\r
-//\r
-#pragma pack ()\r
-\r
-//\r
-// Define pointer types used to access TIS registers on PC\r
-//\r
-typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
-\r
-//\r
-// Define bits of ACCESS and STATUS registers\r
-//\r
-\r
-///\r
-/// This bit is a 1 to indicate that the other bits in this register are valid.\r
-///\r
-#define TIS_PC_VALID BIT7\r
-///\r
-/// Indicate that this locality is active.\r
-///\r
-#define TIS_PC_ACC_ACTIVE BIT5\r
-///\r
-/// Set to 1 to indicate that this locality had the TPM taken away while\r
-/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
-///\r
-#define TIS_PC_ACC_SEIZED BIT4\r
-///\r
-/// Set to 1 to indicate that TPM MUST reset the\r
-/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
-/// locality that is writing this bit.\r
-///\r
-#define TIS_PC_ACC_SEIZE BIT3\r
-///\r
-/// When this bit is 1, another locality is requesting usage of the TPM.\r
-///\r
-#define TIS_PC_ACC_PENDIND BIT2\r
-///\r
-/// Set to 1 to indicate that this locality is requesting to use TPM.\r
-///\r
-#define TIS_PC_ACC_RQUUSE BIT1\r
-///\r
-/// A value of 1 indicates that a T/OS has not been established on the platform\r
-///\r
-#define TIS_PC_ACC_ESTABLISH BIT0\r
-\r
-///\r
-/// When this bit is 1, TPM is in the Ready state, \r
-/// indicating it is ready to receive a new command.\r
-///\r
-#define TIS_PC_STS_READY BIT6\r
-///\r
-/// Write a 1 to this bit to cause the TPM to execute that command.\r
-///\r
-#define TIS_PC_STS_GO BIT5\r
-///\r
-/// This bit indicates that the TPM has data available as a response.\r
-///\r
-#define TIS_PC_STS_DATA BIT4\r
-///\r
-/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
-///\r
-#define TIS_PC_STS_EXPECT BIT3\r
-///\r
-/// Writes a 1 to this bit to force the TPM to re-send the response.\r
-///\r
-#define TIS_PC_STS_RETRY BIT1\r
-\r
-//\r
-// Default TimeOut value\r
-//\r
-#define TIS_TIMEOUT_A (1000 * 1000) // 1s\r
-#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
-#define TIS_TIMEOUT_C (1000 * 1000) // 1s\r
-#define TIS_TIMEOUT_D (1000 * 1000) // 1s\r
+#include <IndustryStandard/TpmTis.h>\r
\r
-#define TIS_TIMEOUT_MAX (90000 * 1000) // 90s\r
+#define TIS_TIMEOUT_MAX (90000 * 1000) // 90s\r
\r
//\r
-// Max TPM command/reponse length\r
+// Max TPM command/response length\r
//\r
-#define TPMCMDBUFLENGTH 0x500\r
+#define TPMCMDBUFLENGTH 0x500\r
\r
/**\r
Check whether TPM chip exist.\r
**/\r
BOOLEAN\r
TisPcPresenceCheck (\r
- IN TIS_PC_REGISTERS_PTR TisReg\r
+ IN TIS_PC_REGISTERS_PTR TisReg\r
)\r
{\r
- UINT8 RegRead;\r
- \r
+ UINT8 RegRead;\r
+\r
RegRead = MmioRead8 ((UINTN)&TisReg->Access);\r
return (BOOLEAN)(RegRead != (UINT8)-1);\r
}\r
**/\r
EFI_STATUS\r
TisPcWaitRegisterBits (\r
- IN UINT8 *Register,\r
- IN UINT8 BitSet,\r
- IN UINT8 BitClear,\r
- IN UINT32 TimeOut\r
+ IN UINT8 *Register,\r
+ IN UINT8 BitSet,\r
+ IN UINT8 BitClear,\r
+ IN UINT32 TimeOut\r
)\r
{\r
- UINT8 RegRead;\r
- UINT32 WaitTime;\r
+ UINT8 RegRead;\r
+ UINT32 WaitTime;\r
\r
- for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
+ for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30) {\r
RegRead = MmioRead8 ((UINTN)Register);\r
- if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r
+ if (((RegRead & BitSet) == BitSet) && ((RegRead & BitClear) == 0)) {\r
return EFI_SUCCESS;\r
+ }\r
+\r
MicroSecondDelay (30);\r
}\r
+\r
return EFI_TIMEOUT;\r
}\r
\r
/**\r
- Get BurstCount by reading the burstCount field of a TIS regiger \r
+ Get BurstCount by reading the burstCount field of a TIS register\r
in the time of default TIS_TIMEOUT_D.\r
\r
@param[in] TisReg Pointer to TIS register.\r
- @param[out] BurstCount Pointer to a buffer to store the got BurstConut.\r
+ @param[out] BurstCount Pointer to a buffer to store the got BurstCount.\r
\r
@retval EFI_SUCCESS Get BurstCount.\r
@retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r
**/\r
EFI_STATUS\r
TisPcReadBurstCount (\r
- IN TIS_PC_REGISTERS_PTR TisReg,\r
- OUT UINT16 *BurstCount\r
+ IN TIS_PC_REGISTERS_PTR TisReg,\r
+ OUT UINT16 *BurstCount\r
)\r
{\r
- UINT32 WaitTime;\r
- UINT8 DataByte0;\r
- UINT8 DataByte1;\r
+ UINT32 WaitTime;\r
+ UINT8 DataByte0;\r
+ UINT8 DataByte1;\r
\r
- if (BurstCount == NULL || TisReg == NULL) {\r
+ if ((BurstCount == NULL) || (TisReg == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if (*BurstCount != 0) {\r
return EFI_SUCCESS;\r
}\r
+\r
MicroSecondDelay (30);\r
WaitTime += 30;\r
} while (WaitTime < TIS_TIMEOUT_D);\r
}\r
\r
/**\r
- Set TPM chip to ready state by sending ready command TIS_PC_STS_READY \r
+ Set TPM chip to ready state by sending ready command TIS_PC_STS_READY\r
to Status Register in time.\r
\r
@param[in] TisReg Pointer to TIS register.\r
**/\r
EFI_STATUS\r
TisPcPrepareCommand (\r
- IN TIS_PC_REGISTERS_PTR TisReg\r
+ IN TIS_PC_REGISTERS_PTR TisReg\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (TisReg == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
+ MmioWrite8 ((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
Status = TisPcWaitRegisterBits (\r
&TisReg->Status,\r
TIS_PC_STS_READY,\r
}\r
\r
/**\r
- Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE \r
+ Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE\r
to ACCESS Register in the time of default TIS_TIMEOUT_A.\r
\r
@param[in] TisReg Pointer to TIS register.\r
**/\r
EFI_STATUS\r
TisPcRequestUseTpm (\r
- IN TIS_PC_REGISTERS_PTR TisReg\r
+ IN TIS_PC_REGISTERS_PTR TisReg\r
)\r
{\r
- EFI_STATUS Status;\r
- \r
+ EFI_STATUS Status;\r
+\r
if (TisReg == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
if (!TisPcPresenceCheck (TisReg)) {\r
return EFI_NOT_FOUND;\r
}\r
\r
- MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r
+ MmioWrite8 ((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r
Status = TisPcWaitRegisterBits (\r
&TisReg->Access,\r
(UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),\r
/**\r
Send a command to TPM for execution and return response data.\r
\r
- @param[in] TisReg TPM register space base address. \r
- @param[in] BufferIn Buffer for command data. \r
- @param[in] SizeIn Size of command data. \r
- @param[in, out] BufferOut Buffer for response data. \r
- @param[in, out] SizeOut Size of response data. \r
- \r
+ @param[in] TisReg TPM register space base address.\r
+ @param[in] BufferIn Buffer for command data.\r
+ @param[in] SizeIn Size of command data.\r
+ @param[in, out] BufferOut Buffer for response data.\r
+ @param[in, out] SizeOut Size of response data.\r
+\r
@retval EFI_SUCCESS Operation completed successfully.\r
@retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r
@retval EFI_DEVICE_ERROR Unexpected device behavior.\r
\r
**/\r
EFI_STATUS\r
-TisTpmCommand (\r
- IN TIS_PC_REGISTERS_PTR TisReg,\r
- IN UINT8 *BufferIn,\r
- IN UINT32 SizeIn,\r
- IN OUT UINT8 *BufferOut,\r
- IN OUT UINT32 *SizeOut\r
+Tpm2TisTpmCommand (\r
+ IN TIS_PC_REGISTERS_PTR TisReg,\r
+ IN UINT8 *BufferIn,\r
+ IN UINT32 SizeIn,\r
+ IN OUT UINT8 *BufferOut,\r
+ IN OUT UINT32 *SizeOut\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT16 BurstCount;\r
- UINT32 Index;\r
- UINT32 TpmOutSize;\r
- UINT16 Data16;\r
- UINT32 Data32;\r
-\r
- DEBUG_CODE (\r
- UINTN DebugSize;\r
-\r
- DEBUG ((EFI_D_INFO, "Tpm2TisTpmCommand Send - "));\r
- if (SizeIn > 0x100) {\r
- DebugSize = 0x40;\r
- } else {\r
- DebugSize = SizeIn;\r
- }\r
- for (Index = 0; Index < DebugSize; Index++) {\r
- DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));\r
- }\r
- if (DebugSize != SizeIn) {\r
- DEBUG ((EFI_D_INFO, "...... "));\r
- for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r
- DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));\r
- }\r
+ EFI_STATUS Status;\r
+ UINT16 BurstCount;\r
+ UINT32 Index;\r
+ UINT32 TpmOutSize;\r
+ UINT16 Data16;\r
+ UINT32 Data32;\r
+\r
+ DEBUG_CODE_BEGIN ();\r
+ UINTN DebugSize;\r
+\r
+ DEBUG ((DEBUG_VERBOSE, "Tpm2TisTpmCommand Send - "));\r
+ if (SizeIn > 0x100) {\r
+ DebugSize = 0x40;\r
+ } else {\r
+ DebugSize = SizeIn;\r
+ }\r
+\r
+ for (Index = 0; Index < DebugSize; Index++) {\r
+ DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));\r
+ }\r
+\r
+ if (DebugSize != SizeIn) {\r
+ DEBUG ((DEBUG_VERBOSE, "...... "));\r
+ for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r
+ DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));\r
}\r
- DEBUG ((EFI_D_INFO, "\n"));\r
- );\r
+ }\r
+\r
+ DEBUG ((DEBUG_VERBOSE, "\n"));\r
+ DEBUG_CODE_END ();\r
TpmOutSize = 0;\r
\r
Status = TisPcPrepareCommand (TisReg);\r
- if (EFI_ERROR (Status)){\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "Tpm2 is not ready for command!\n"));\r
return EFI_DEVICE_ERROR;\r
}\r
+\r
//\r
// Send the command data to Tpm\r
//\r
Status = EFI_DEVICE_ERROR;\r
goto Exit;\r
}\r
- for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r
- MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r
+\r
+ for ( ; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r
+ MmioWrite8 ((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r
Index++;\r
}\r
}\r
+\r
//\r
// Check the Tpm status STS_EXPECT change from 1 to 0\r
//\r
Status = TisPcWaitRegisterBits (\r
&TisReg->Status,\r
- (UINT8) TIS_PC_VALID,\r
+ (UINT8)TIS_PC_VALID,\r
TIS_PC_STS_EXPECT,\r
TIS_TIMEOUT_C\r
);\r
Status = EFI_BUFFER_TOO_SMALL;\r
goto Exit;\r
}\r
+\r
//\r
// Executed the TPM command and waiting for the response data ready\r
//\r
- MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r
+ MmioWrite8 ((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r
\r
//\r
// NOTE: That may take many seconds to minutes for certain commands, such as key generation.\r
//\r
Status = TisPcWaitRegisterBits (\r
&TisReg->Status,\r
- (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),\r
+ (UINT8)(TIS_PC_VALID | TIS_PC_STS_DATA),\r
0,\r
TIS_TIMEOUT_MAX\r
);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out!!\n"));\r
- Status = EFI_DEVICE_ERROR;\r
- goto Exit;\r
+ //\r
+ // dataAvail check timeout. Cancel the currently executing command by writing commandCancel,\r
+ // Expect TPM_RC_CANCELLED or successfully completed response.\r
+ //\r
+ DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out. Trying to cancel the command!!\n"));\r
+\r
+ MmioWrite32 ((UINTN)&TisReg->Status, TIS_PC_STS_CANCEL);\r
+ Status = TisPcWaitRegisterBits (\r
+ &TisReg->Status,\r
+ (UINT8)(TIS_PC_VALID | TIS_PC_STS_DATA),\r
+ 0,\r
+ TIS_TIMEOUT_B\r
+ );\r
+ //\r
+ // Do not clear CANCEL bit here because Writes of 0 to this bit are ignored\r
+ //\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Cancel executing command fail to get any response\r
+ // Try to abort the command with write of a 1 to commandReady in Command Execution state\r
+ //\r
+ Status = EFI_DEVICE_ERROR;\r
+ goto Exit;\r
+ }\r
}\r
+\r
//\r
// Get response data header\r
//\r
- Index = 0;\r
+ Index = 0;\r
BurstCount = 0;\r
while (Index < sizeof (TPM2_RESPONSE_HEADER)) {\r
Status = TisPcReadBurstCount (TisReg, &BurstCount);\r
Status = EFI_DEVICE_ERROR;\r
goto Exit;\r
}\r
- for (; BurstCount > 0; BurstCount--) {\r
+\r
+ for ( ; BurstCount > 0; BurstCount--) {\r
*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
Index++;\r
- if (Index == sizeof (TPM2_RESPONSE_HEADER)) break;\r
+ if (Index == sizeof (TPM2_RESPONSE_HEADER)) {\r
+ break;\r
+ }\r
}\r
}\r
- DEBUG_CODE (\r
- DEBUG ((EFI_D_INFO, "TisTpmCommand ReceiveHeader - "));\r
- for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r
- DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));\r
- }\r
- DEBUG ((EFI_D_INFO, "\n"));\r
- );\r
+\r
+ DEBUG_CODE_BEGIN ();\r
+ DEBUG ((DEBUG_VERBOSE, "Tpm2TisTpmCommand ReceiveHeader - "));\r
+ for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r
+ DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));\r
+ }\r
+\r
+ DEBUG ((DEBUG_VERBOSE, "\n"));\r
+ DEBUG_CODE_END ();\r
//\r
- // Check the reponse data header (tag,parasize and returncode )\r
+ // Check the response data header (tag,parasize and returncode )\r
//\r
CopyMem (&Data16, BufferOut, sizeof (UINT16));\r
// TPM2 should not use this RSP_COMMAND\r
if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {\r
- DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));\r
+ DEBUG ((DEBUG_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));\r
Status = EFI_UNSUPPORTED;\r
goto Exit;\r
}\r
\r
CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r
- TpmOutSize = SwapBytes32 (Data32);\r
+ TpmOutSize = SwapBytes32 (Data32);\r
if (*SizeOut < TpmOutSize) {\r
Status = EFI_BUFFER_TOO_SMALL;\r
goto Exit;\r
}\r
+\r
*SizeOut = TpmOutSize;\r
//\r
// Continue reading the remaining data\r
//\r
while ( Index < TpmOutSize ) {\r
- for (; BurstCount > 0; BurstCount--) {\r
+ for ( ; BurstCount > 0; BurstCount--) {\r
*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
Index++;\r
if (Index == TpmOutSize) {\r
goto Exit;\r
}\r
}\r
+\r
Status = TisPcReadBurstCount (TisReg, &BurstCount);\r
if (EFI_ERROR (Status)) {\r
Status = EFI_DEVICE_ERROR;\r
goto Exit;\r
}\r
}\r
+\r
Exit:\r
- DEBUG_CODE (\r
- DEBUG ((EFI_D_INFO, "Tpm2TisTpmCommand Receive - "));\r
- for (Index = 0; Index < TpmOutSize; Index++) {\r
- DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));\r
- }\r
- DEBUG ((EFI_D_INFO, "\n"));\r
- );\r
- MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
+ DEBUG_CODE_BEGIN ();\r
+ DEBUG ((DEBUG_VERBOSE, "Tpm2TisTpmCommand Receive - "));\r
+ for (Index = 0; Index < TpmOutSize; Index++) {\r
+ DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));\r
+ }\r
+\r
+ DEBUG ((DEBUG_VERBOSE, "\n"));\r
+ DEBUG_CODE_END ();\r
+ MmioWrite8 ((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
return Status;\r
}\r
\r
\r
@retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r
@retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r
- @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small. \r
+ @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DTpm2SubmitCommand (\r
- IN UINT32 InputParameterBlockSize,\r
- IN UINT8 *InputParameterBlock,\r
- IN OUT UINT32 *OutputParameterBlockSize,\r
- IN UINT8 *OutputParameterBlock\r
+DTpm2TisSubmitCommand (\r
+ IN UINT32 InputParameterBlockSize,\r
+ IN UINT8 *InputParameterBlock,\r
+ IN OUT UINT32 *OutputParameterBlockSize,\r
+ IN UINT8 *OutputParameterBlock\r
)\r
{\r
- return TisTpmCommand (\r
- (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r
+ return Tpm2TisTpmCommand (\r
+ (TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress),\r
InputParameterBlock,\r
InputParameterBlockSize,\r
OutputParameterBlock,\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DTpm2RequestUseTpm (\r
+DTpm2TisRequestUseTpm (\r
VOID\r
)\r
{\r
- return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
+ return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress));\r
}\r
projects / mirror_edk2.git / blobdiff