/** @file\r
- The TPM2 definition block in ACPI table for TCG2 physical presence \r
+ The TPM2 definition block in ACPI table for TCG2 physical presence\r
and MemoryClear.\r
\r
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
+(c)Copyright 2016 HP Development Company, L.P.<BR>\r
+Copyright (c) 2017, Microsoft Corporation. All rights reserved. <BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
//\r
// TCG2\r
//\r
- Name (_HID, "MSFT0101")\r
- \r
+\r
//\r
- // Readable name of this device, don't know if this way is correct yet\r
+ // TAG for patching TPM2.0 _HID\r
//\r
- Name (_STR, Unicode ("TPM 2.0 Device"))\r
+ Name (_HID, "NNNN0000")\r
+\r
+ Name (_CID, "MSFT0101")\r
\r
//\r
- // Return the resource consumed by TPM device\r
+ // Readable name of this device, don't know if this way is correct yet\r
//\r
- Name (_CRS, ResourceTemplate () {\r
- Memory32Fixed (ReadOnly, 0xfed40000, 0x5000)\r
- })\r
+ Name (_STR, Unicode ("TPM 2.0 Device"))\r
\r
//\r
// Operational region for Smi port access\r
//\r
OperationRegion (SMIP, SystemIO, 0xB2, 1)\r
Field (SMIP, ByteAcc, NoLock, Preserve)\r
- { \r
+ {\r
IOB2, 8\r
}\r
\r
OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)\r
Field (TPMR, AnyAcc, NoLock, Preserve)\r
{\r
- ACC0, 8,\r
+ ACC0, 8, // TPM_ACCESS_0\r
+ Offset(0x8),\r
+ INTE, 32, // TPM_INT_ENABLE_0\r
+ INTV, 8, // TPM_INT_VECTOR_0\r
+ Offset(0x10),\r
+ INTS, 32, // TPM_INT_STATUS_0\r
+ INTF, 32, // TPM_INTF_CAPABILITY_0\r
+ STS0, 32, // TPM_STS_0\r
+ Offset(0x24),\r
+ FIFO, 32, // TPM_DATA_FIFO_0\r
+ Offset(0x30),\r
+ TID0, 32, // TPM_INTERFACE_ID_0\r
+ // ignore the rest\r
}\r
\r
//\r
MCIN, 8, // Software SMI for Memory Clear Interface\r
MCIP, 32, // Used for save the Mor paramter\r
MORD, 32, // Memory Overwrite Request Data\r
- MRET, 32 // Memory Overwrite function return code\r
+ MRET, 32, // Memory Overwrite function return code\r
+ UCRQ, 32, // Phyical Presence request operation to Get User Confirmation Status\r
+ IRQN, 32, // IRQ Number for _CRS\r
+ SFRB, 8 // Is shortformed Pkglength for resource buffer\r
+ }\r
+\r
+ //\r
+ // Possible resource settings returned by _PRS method\r
+ // RESS : ResourceTemplate with PkgLength <=63\r
+ // RESL : ResourceTemplate with PkgLength > 63\r
+ //\r
+ // The format of the data has to follow the same format as\r
+ // _CRS (according to ACPI spec).\r
+ //\r
+ Name (RESS, ResourceTemplate() {\r
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10}\r
+ })\r
+\r
+ Name (RESL, ResourceTemplate() {\r
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}\r
+ })\r
+\r
+ //\r
+ // Current resource settings for _CRS method\r
+ //\r
+ Name(RES0, ResourceTemplate () {\r
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG0)\r
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , INTR) {12}\r
+ })\r
+\r
+ Name(RES1, ResourceTemplate () {\r
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG1)\r
+ })\r
+\r
+\r
+ //\r
+ // Return the resource consumed by TPM device.\r
+ //\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ //\r
+ // IRQNum = 0 means disable IRQ support\r
+ //\r
+ If (LEqual(IRQN, 0)) {\r
+ Return (RES1)\r
+ }\r
+ Else\r
+ {\r
+ CreateDWordField(RES0, ^INTR._INT, LIRQ)\r
+ Store(IRQN, LIRQ)\r
+ Return (RES0)\r
+ }\r
+ }\r
+\r
+ //\r
+ // Set resources consumed by the TPM device. This is used to\r
+ // assign an interrupt number to the device. The input byte stream\r
+ // has to be the same as returned by _CRS (according to ACPI spec).\r
+ //\r
+ // Platform may choose to override this function with specific interrupt\r
+ // programing logic to replace FIFO/TIS SIRQ registers programing\r
+ //\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ //\r
+ // Do not configure Interrupt if IRQ Num is configured 0 by default\r
+ //\r
+ If (LNotEqual(IRQN, 0)) {\r
+ //\r
+ // Update resource descriptor\r
+ // Use the field name to identify the offsets in the argument\r
+ // buffer and RES0 buffer.\r
+ //\r
+ CreateDWordField(Arg0, ^INTR._INT, IRQ0)\r
+ CreateDWordField(RES0, ^INTR._INT, LIRQ)\r
+ Store(IRQ0, LIRQ)\r
+ Store(IRQ0, IRQN)\r
+\r
+ CreateBitField(Arg0, ^INTR._HE, ITRG)\r
+ CreateBitField(RES0, ^INTR._HE, LTRG)\r
+ Store(ITRG, LTRG)\r
+\r
+ CreateBitField(Arg0, ^INTR._LL, ILVL)\r
+ CreateBitField(RES0, ^INTR._LL, LLVL)\r
+ Store(ILVL, LLVL)\r
+\r
+ //\r
+ // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest\r
+ // nibble.\r
+ // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active\r
+ // 1111 - FIFO interface as defined in TIS1.3 is active\r
+ //\r
+ If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {\r
+ //\r
+ // If FIFO interface, interrupt vector register is\r
+ // available. TCG PTP specification allows only\r
+ // values 1..15 in this field. For other interrupts\r
+ // the field should stay 0.\r
+ //\r
+ If (LLess (IRQ0, 16)) {\r
+ Store (And(IRQ0, 0xF), INTV)\r
+ }\r
+ //\r
+ // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4\r
+ // contains settings for interrupt polarity.\r
+ // The other bits of the byte enable individual interrupts.\r
+ // They should be all be zero, but to avoid changing the\r
+ // configuration, the other bits are be preserved.\r
+ // 00 - high level\r
+ // 01 - low level\r
+ // 10 - rising edge\r
+ // 11 - falling edge\r
+ //\r
+ // ACPI spec definitions:\r
+ // _HE: '1' is Edge, '0' is Level\r
+ // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)\r
+ //\r
+ If (LEqual (ITRG, 1)) {\r
+ Or(INTE, 0x00000010, INTE)\r
+ } Else {\r
+ And(INTE, 0xFFFFFFEF, INTE)\r
+ }\r
+ if (LEqual (ILVL, 0)) {\r
+ Or(INTE, 0x00000008, INTE)\r
+ } Else {\r
+ And(INTE, 0xFFFFFFF7, INTE)\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ Method(_PRS,0,Serialized)\r
+ {\r
+ //\r
+ // IRQNum = 0 means disable IRQ support\r
+ //\r
+ If (LEqual(IRQN, 0)) {\r
+ Return (RES1)\r
+ } ElseIf(LEqual(SFRB, 0)) {\r
+ //\r
+ // Long format. Possible resources PkgLength > 63\r
+ //\r
+ Return (RESL)\r
+ } Else {\r
+ //\r
+ // Short format. Possible resources PkgLength <=63\r
+ //\r
+ Return (RESS)\r
+ }\r
}\r
\r
Method (PTS, 1, Serialized)\r
- { \r
+ {\r
//\r
// Detect Sx state for MOR, only S4, S5 need to handle\r
//\r
If (LAnd (LLess (Arg0, 6), LGreater (Arg0, 3)))\r
- { \r
+ {\r
//\r
// Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect.\r
//\r
If (LNot (And (MORD, 0x10)))\r
{\r
//\r
- // Triggle the SMI through ACPI _PTS method.\r
+ // Trigger the SMI through ACPI _PTS method.\r
//\r
Store (0x02, MCIP)\r
- \r
+\r
//\r
- // Triggle the SMI interrupt\r
+ // Trigger the SMI interrupt\r
//\r
Store (MCIN, IOB2)\r
}\r
}\r
Return (0)\r
- } \r
+ }\r
\r
Method (_STA, 0)\r
{\r
//\r
// TCG Hardware Information\r
//\r
- Method (HINF, 3, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
+ Method (HINF, 1, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj}) // IntObj\r
{\r
//\r
// Switch by function index\r
//\r
- Switch (ToInteger(Arg1))\r
+ Switch (ToInteger(Arg0))\r
{\r
Case (0)\r
{\r
}\r
\r
Name(TPM2, Package (0x02){\r
- Zero, \r
+ Zero,\r
Zero\r
})\r
\r
Name(TPM3, Package (0x03){\r
- Zero, \r
+ Zero,\r
Zero,\r
Zero\r
})\r
//\r
// TCG Physical Presence Interface\r
//\r
- Method (TPPI, 3, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
- { \r
+ Method (TPPI, 2, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj}) // IntObj, PkgObj\r
+ {\r
//\r
// Switch by function index\r
//\r
- Switch (ToInteger(Arg1))\r
+ Switch (ToInteger(Arg0))\r
{\r
Case (0)\r
{\r
//\r
// a) Get Physical Presence Interface Version\r
//\r
- Return ("1.2")\r
+ Return ("$PV")\r
}\r
Case (2)\r
{\r
//\r
// b) Submit TPM Operation Request to Pre-OS Environment\r
//\r
- \r
- Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
+\r
+ Store (DerefOf (Index (Arg1, 0x00)), PPRQ)\r
+ Store (0, PPRM)\r
Store (0x02, PPIP)\r
- \r
+\r
//\r
- // Triggle the SMI interrupt\r
+ // Trigger the SMI interrupt\r
//\r
Store (PPIN, IOB2)\r
Return (FRET)\r
//\r
// c) Get Pending TPM Operation Requested By the OS\r
//\r
- \r
+\r
Store (PPRQ, Index (TPM2, 0x01))\r
Return (TPM2)\r
}\r
// e) Return TPM Operation Response to OS Environment\r
//\r
Store (0x05, PPIP)\r
- \r
+\r
//\r
- // Triggle the SMI interrupt\r
+ // Trigger the SMI interrupt\r
//\r
Store (PPIN, IOB2)\r
- \r
+\r
Store (LPPR, Index (TPM3, 0x01))\r
Store (PPRP, Index (TPM3, 0x02))\r
\r
// g) Submit TPM Operation Request to Pre-OS Environment 2\r
//\r
Store (7, PPIP)\r
- Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
+ Store (DerefOf (Index (Arg1, 0x00)), PPRQ)\r
Store (0, PPRM)\r
If (LEqual (PPRQ, 23)) {\r
- Store (DerefOf (Index (Arg2, 0x01)), PPRM)\r
+ Store (DerefOf (Index (Arg1, 0x01)), PPRM)\r
}\r
- \r
+\r
//\r
- // Triggle the SMI interrupt \r
+ // Trigger the SMI interrupt\r
//\r
- Store (PPIN, IOB2) \r
+ Store (PPIN, IOB2)\r
Return (FRET)\r
}\r
Case (8)\r
// e) Get User Confirmation Status for Operation\r
//\r
Store (8, PPIP)\r
- Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
- \r
+ Store (DerefOf (Index (Arg1, 0x00)), UCRQ)\r
+\r
//\r
- // Triggle the SMI interrupt\r
+ // Trigger the SMI interrupt\r
//\r
Store (PPIN, IOB2)\r
- \r
+\r
Return (FRET)\r
}\r
\r
Return (1)\r
}\r
\r
- Method (TMCI, 3, Serialized, 0, IntObj, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
+ Method (TMCI, 2, Serialized, 0, IntObj, {UnknownObj, UnknownObj}) // IntObj, PkgObj\r
{\r
//\r
// Switch by function index\r
//\r
- Switch (ToInteger (Arg1))\r
+ Switch (ToInteger (Arg0))\r
{\r
Case (0)\r
{\r
//\r
// Save the Operation Value of the Request to MORD (reserved memory)\r
//\r
- Store (DerefOf (Index (Arg2, 0x00)), MORD)\r
- \r
+ Store (DerefOf (Index (Arg1, 0x00)), MORD)\r
+\r
//\r
- // Triggle the SMI through ACPI _DSM method.\r
+ // Trigger the SMI through ACPI _DSM method.\r
//\r
Store (0x01, MCIP)\r
- \r
+\r
//\r
- // Triggle the SMI interrupt\r
+ // Trigger the SMI interrupt\r
//\r
Store (MCIN, IOB2)\r
Return (MRET)\r
}\r
Default {BreakPoint}\r
}\r
- Return (1) \r
+ Return (1)\r
}\r
\r
Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})\r
//\r
If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))\r
{\r
- Return (HINF (Arg1, Arg2, Arg3))\r
+ Return (HINF (Arg2))\r
}\r
\r
//\r
//\r
If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))\r
{\r
- Return (TPPI (Arg1, Arg2, Arg3))\r
+ Return (TPPI (Arg2, Arg3))\r
}\r
\r
//\r
//\r
If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))\r
{\r
- Return (TMCI (Arg1, Arg2, Arg3))\r
+ Return (TMCI (Arg2, Arg3))\r
}\r
\r
Return (Buffer () {0})\r
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