///\r
/// Level 3 base server system Private Peripheral Inerrupt (PPI) ID assignments\r
///\r
-#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTP 30\r
-#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTPS 29\r
-#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTHV 28\r
-#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTV 27\r
-#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTHP 26\r
-#define ARM_PPI_ID_GIC_MAINTENANCE_INTERRUPT 25\r
-#define ARM_PPI_ID_CTIIRQ 24\r
-#define ARM_PPI_ID_PERFORMANCE_MONITORS_INTERRUPT 23\r
-#define ARM_PPI_ID_COMMIRQ 22\r
-#define ARM_PPI_ID_PMBIRQ 21\r
-#define ARM_PPI_ID_CNTHPS 20\r
-#define ARM_PPI_ID_CNTHVS 19\r
+#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTP 30\r
+#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTPS 29\r
+#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTHV 28\r
+#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTV 27\r
+#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTHP 26\r
+#define ARM_PPI_ID_GIC_MAINTENANCE_INTERRUPT 25\r
+#define ARM_PPI_ID_CTIIRQ 24\r
+#define ARM_PPI_ID_PERFORMANCE_MONITORS_INTERRUPT 23\r
+#define ARM_PPI_ID_COMMIRQ 22\r
+#define ARM_PPI_ID_PMBIRQ 21\r
+#define ARM_PPI_ID_CNTHPS 20\r
+#define ARM_PPI_ID_CNTHVS 19\r
\r
///\r
/// PPI ID allowed ranges\r
///\r
-#define ARM_PPI_ID_MAX 31\r
-#define ARM_PPI_ID_MIN 16\r
-#define ARM_PPI_ID_EXTENDED_MAX 1119\r
-#define ARM_PPI_ID_EXTENDED_MIN 1056\r
+#define ARM_PPI_ID_MAX 31\r
+#define ARM_PPI_ID_MIN 16\r
+#define ARM_PPI_ID_EXTENDED_MAX 1119\r
+#define ARM_PPI_ID_EXTENDED_MIN 1056\r
\r
#endif // MADT_PARSER_H_\r