ShellMmPciExpress\r
} SHELL_MM_ACCESS_TYPE;\r
\r
-CONST UINT16 mShellMmAccessTypeStr[] = {\r
+CONST UINT16 mShellMmAccessTypeStr[] = {\r
STRING_TOKEN (STR_MM_MEM),\r
STRING_TOKEN (STR_MM_MMIO),\r
STRING_TOKEN (STR_MM_IO),\r
STRING_TOKEN (STR_MM_PCIE)\r
};\r
\r
-STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
- {L"-mmio", TypeFlag},\r
- {L"-mem", TypeFlag},\r
- {L"-io", TypeFlag},\r
- {L"-pci", TypeFlag},\r
- {L"-pcie", TypeFlag},\r
- {L"-n", TypeFlag},\r
- {L"-w", TypeValue},\r
- {NULL, TypeMax}\r
- };\r
-\r
-CONST UINT64 mShellMmMaxNumber[] = {\r
+STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
+ { L"-mmio", TypeFlag },\r
+ { L"-mem", TypeFlag },\r
+ { L"-io", TypeFlag },\r
+ { L"-pci", TypeFlag },\r
+ { L"-pcie", TypeFlag },\r
+ { L"-n", TypeFlag },\r
+ { L"-w", TypeValue },\r
+ { NULL, TypeMax }\r
+};\r
+\r
+CONST UINT64 mShellMmMaxNumber[] = {\r
0, MAX_UINT8, MAX_UINT16, 0, MAX_UINT32, 0, 0, 0, MAX_UINT64\r
};\r
-CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH mShellMmRootBridgeIoWidth[] = {\r
+CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH mShellMmRootBridgeIoWidth[] = {\r
0, EfiPciWidthUint8, EfiPciWidthUint16, 0, EfiPciWidthUint32, 0, 0, 0, EfiPciWidthUint64\r
};\r
-CONST EFI_CPU_IO_PROTOCOL_WIDTH mShellMmCpuIoWidth[] = {\r
+CONST EFI_CPU_IO_PROTOCOL_WIDTH mShellMmCpuIoWidth[] = {\r
0, EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, 0, EfiCpuIoWidthUint32, 0, 0, 0, EfiCpuIoWidthUint64\r
};\r
\r
**/\r
VOID\r
ShellMmDecodePciAddress (\r
- IN BOOLEAN PciFormat,\r
- IN UINT64 Address,\r
- OUT UINT32 *Segment,\r
- OUT UINT8 *Bus,\r
- OUT UINT8 *Device OPTIONAL,\r
- OUT UINT8 *Function OPTIONAL,\r
- OUT UINT32 *Register OPTIONAL\r
+ IN BOOLEAN PciFormat,\r
+ IN UINT64 Address,\r
+ OUT UINT32 *Segment,\r
+ OUT UINT8 *Bus,\r
+ OUT UINT8 *Device OPTIONAL,\r
+ OUT UINT8 *Function OPTIONAL,\r
+ OUT UINT32 *Register OPTIONAL\r
)\r
{\r
if (PciFormat) {\r
// PCI Configuration Space.The address will have the format ssssbbddffrr,\r
// where ssss = Segment, bb = Bus, dd = Device, ff = Function and rr = Register.\r
//\r
- *Segment = (UINT32) (RShiftU64 (Address, 32) & 0xFFFF);\r
- *Bus = (UINT8) (((UINT32) Address) >> 24);\r
+ *Segment = (UINT32)(RShiftU64 (Address, 32) & 0xFFFF);\r
+ *Bus = (UINT8)(((UINT32)Address) >> 24);\r
\r
if (Device != NULL) {\r
- *Device = (UINT8) (((UINT32) Address) >> 16);\r
+ *Device = (UINT8)(((UINT32)Address) >> 16);\r
}\r
+\r
if (Function != NULL) {\r
- *Function = (UINT8) (((UINT32) Address) >> 8);\r
+ *Function = (UINT8)(((UINT32)Address) >> 8);\r
}\r
+\r
if (Register != NULL) {\r
- *Register = (UINT8) Address;\r
+ *Register = (UINT8)Address;\r
}\r
} else {\r
//\r
// PCI Express Configuration Space.The address will have the format ssssssbbddffrrr,\r
// where ssss = Segment, bb = Bus, dd = Device, ff = Function and rrr = Register.\r
//\r
- *Segment = (UINT32) (RShiftU64 (Address, 36) & 0xFFFF);\r
- *Bus = (UINT8) RShiftU64 (Address, 28);\r
+ *Segment = (UINT32)(RShiftU64 (Address, 36) & 0xFFFF);\r
+ *Bus = (UINT8)RShiftU64 (Address, 28);\r
if (Device != NULL) {\r
- *Device = (UINT8) (((UINT32) Address) >> 20);\r
+ *Device = (UINT8)(((UINT32)Address) >> 20);\r
}\r
+\r
if (Function != NULL) {\r
- *Function = (UINT8) (((UINT32) Address) >> 12);\r
+ *Function = (UINT8)(((UINT32)Address) >> 12);\r
}\r
+\r
if (Register != NULL) {\r
- *Register = (UINT32) (Address & 0xFFF);\r
+ *Register = (UINT32)(Address & 0xFFF);\r
}\r
}\r
}\r
**/\r
VOID\r
ShellMmAccess (\r
- IN SHELL_MM_ACCESS_TYPE AccessType,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN EFI_CPU_IO2_PROTOCOL *CpuIo,\r
- IN BOOLEAN Read,\r
- IN UINT64 Address,\r
- IN UINTN Size,\r
- IN OUT VOID *Buffer\r
+ IN SHELL_MM_ACCESS_TYPE AccessType,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
+ IN EFI_CPU_IO2_PROTOCOL *CpuIo,\r
+ IN BOOLEAN Read,\r
+ IN UINT64 Address,\r
+ IN UINTN Size,\r
+ IN OUT VOID *Buffer\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM RootBridgeIoMem;\r
- EFI_CPU_IO_PROTOCOL_IO_MEM CpuIoMem;\r
- UINT32 Segment;\r
- UINT8 Bus;\r
- UINT8 Device;\r
- UINT8 Function;\r
- UINT32 Register;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM RootBridgeIoMem;\r
+ EFI_CPU_IO_PROTOCOL_IO_MEM CpuIoMem;\r
+ UINT32 Segment;\r
+ UINT8 Bus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
+ UINT32 Register;\r
\r
if (AccessType == ShellMmMemory) {\r
if (Read) {\r
- CopyMem (Buffer, (VOID *) (UINTN) Address, Size);\r
+ CopyMem (Buffer, (VOID *)(UINTN)Address, Size);\r
} else {\r
- CopyMem ((VOID *) (UINTN) Address, Buffer, Size);\r
+ CopyMem ((VOID *)(UINTN)Address, Buffer, Size);\r
}\r
} else {\r
RootBridgeIoMem = NULL;\r
- CpuIoMem = NULL;\r
+ CpuIoMem = NULL;\r
switch (AccessType) {\r
- case ShellMmPci:\r
- case ShellMmPciExpress:\r
- ASSERT (PciRootBridgeIo != NULL);\r
- ShellMmDecodePciAddress ((BOOLEAN) (AccessType == ShellMmPci), Address, &Segment, &Bus, &Device, &Function, &Register);\r
- if (Read) {\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo, mShellMmRootBridgeIoWidth[Size],\r
- EFI_PCI_ADDRESS (Bus, Device, Function, Register),\r
- 1, Buffer\r
- );\r
- } else {\r
- Status = PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo, mShellMmRootBridgeIoWidth[Size],\r
- EFI_PCI_ADDRESS (Bus, Device, Function, Register),\r
- 1, Buffer\r
- );\r
- }\r
- ASSERT_EFI_ERROR (Status);\r
- return;\r
+ case ShellMmPci:\r
+ case ShellMmPciExpress:\r
+ ASSERT (PciRootBridgeIo != NULL);\r
+ ShellMmDecodePciAddress ((BOOLEAN)(AccessType == ShellMmPci), Address, &Segment, &Bus, &Device, &Function, &Register);\r
+ if (Read) {\r
+ Status = PciRootBridgeIo->Pci.Read (\r
+ PciRootBridgeIo,\r
+ mShellMmRootBridgeIoWidth[Size],\r
+ EFI_PCI_ADDRESS (Bus, Device, Function, Register),\r
+ 1,\r
+ Buffer\r
+ );\r
+ } else {\r
+ Status = PciRootBridgeIo->Pci.Write (\r
+ PciRootBridgeIo,\r
+ mShellMmRootBridgeIoWidth[Size],\r
+ EFI_PCI_ADDRESS (Bus, Device, Function, Register),\r
+ 1,\r
+ Buffer\r
+ );\r
+ }\r
\r
- case ShellMmMemoryMappedIo:\r
- if (PciRootBridgeIo != NULL) {\r
- RootBridgeIoMem = Read ? PciRootBridgeIo->Mem.Read : PciRootBridgeIo->Mem.Write;\r
- }\r
- if (CpuIo != NULL) {\r
- CpuIoMem = Read ? CpuIo->Mem.Read : CpuIo->Mem.Write;\r
- }\r
- break;\r
+ ASSERT_EFI_ERROR (Status);\r
+ return;\r
\r
- case ShellMmIo:\r
- if (PciRootBridgeIo != NULL) {\r
- RootBridgeIoMem = Read ? PciRootBridgeIo->Io.Read : PciRootBridgeIo->Io.Write;\r
- }\r
- if (CpuIo != NULL) {\r
- CpuIoMem = Read ? CpuIo->Io.Read : CpuIo->Io.Write;\r
- }\r
- break;\r
- default:\r
- ASSERT (FALSE);\r
- break;\r
+ case ShellMmMemoryMappedIo:\r
+ if (PciRootBridgeIo != NULL) {\r
+ RootBridgeIoMem = Read ? PciRootBridgeIo->Mem.Read : PciRootBridgeIo->Mem.Write;\r
+ }\r
+\r
+ if (CpuIo != NULL) {\r
+ CpuIoMem = Read ? CpuIo->Mem.Read : CpuIo->Mem.Write;\r
+ }\r
+\r
+ break;\r
+\r
+ case ShellMmIo:\r
+ if (PciRootBridgeIo != NULL) {\r
+ RootBridgeIoMem = Read ? PciRootBridgeIo->Io.Read : PciRootBridgeIo->Io.Write;\r
+ }\r
+\r
+ if (CpuIo != NULL) {\r
+ CpuIoMem = Read ? CpuIo->Io.Read : CpuIo->Io.Write;\r
+ }\r
+\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
\r
Status = EFI_UNSUPPORTED;\r
if (RootBridgeIoMem != NULL) {\r
Status = RootBridgeIoMem (PciRootBridgeIo, mShellMmRootBridgeIoWidth[Size], Address, 1, Buffer);\r
}\r
+\r
if (EFI_ERROR (Status) && (CpuIoMem != NULL)) {\r
Status = CpuIoMem (CpuIo, mShellMmCpuIoWidth[Size], Address, 1, Buffer);\r
}\r
if (EFI_ERROR (Status)) {\r
if (AccessType == ShellMmIo) {\r
switch (Size) {\r
- case 1:\r
- if (Read) {\r
- *(UINT8 *) Buffer = IoRead8 ((UINTN) Address);\r
- } else {\r
- IoWrite8 ((UINTN) Address, *(UINT8 *) Buffer);\r
- }\r
- break;\r
- case 2:\r
- if (Read) {\r
- *(UINT16 *) Buffer = IoRead16 ((UINTN) Address);\r
- } else {\r
- IoWrite16 ((UINTN) Address, *(UINT16 *) Buffer);\r
- }\r
- break;\r
- case 4:\r
- if (Read) {\r
- *(UINT32 *) Buffer = IoRead32 ((UINTN) Address);\r
- } else {\r
- IoWrite32 ((UINTN) Address, *(UINT32 *) Buffer);\r
- }\r
- break;\r
- case 8:\r
- if (Read) {\r
- *(UINT64 *) Buffer = IoRead64 ((UINTN) Address);\r
- } else {\r
- IoWrite64 ((UINTN) Address, *(UINT64 *) Buffer);\r
- }\r
- break;\r
- default:\r
- ASSERT (FALSE);\r
- break;\r
+ case 1:\r
+ if (Read) {\r
+ *(UINT8 *)Buffer = IoRead8 ((UINTN)Address);\r
+ } else {\r
+ IoWrite8 ((UINTN)Address, *(UINT8 *)Buffer);\r
+ }\r
+\r
+ break;\r
+ case 2:\r
+ if (Read) {\r
+ *(UINT16 *)Buffer = IoRead16 ((UINTN)Address);\r
+ } else {\r
+ IoWrite16 ((UINTN)Address, *(UINT16 *)Buffer);\r
+ }\r
+\r
+ break;\r
+ case 4:\r
+ if (Read) {\r
+ *(UINT32 *)Buffer = IoRead32 ((UINTN)Address);\r
+ } else {\r
+ IoWrite32 ((UINTN)Address, *(UINT32 *)Buffer);\r
+ }\r
+\r
+ break;\r
+ case 8:\r
+ if (Read) {\r
+ *(UINT64 *)Buffer = IoRead64 ((UINTN)Address);\r
+ } else {\r
+ IoWrite64 ((UINTN)Address, *(UINT64 *)Buffer);\r
+ }\r
+\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
} else {\r
switch (Size) {\r
- case 1:\r
- if (Read) {\r
- *(UINT8 *) Buffer = MmioRead8 ((UINTN) Address);\r
- } else {\r
- MmioWrite8 ((UINTN) Address, *(UINT8 *) Buffer);\r
- }\r
- break;\r
- case 2:\r
- if (Read) {\r
- *(UINT16 *) Buffer = MmioRead16 ((UINTN) Address);\r
- } else {\r
- MmioWrite16 ((UINTN) Address, *(UINT16 *) Buffer);\r
- }\r
- break;\r
- case 4:\r
- if (Read) {\r
- *(UINT32 *) Buffer = MmioRead32 ((UINTN) Address);\r
- } else {\r
- MmioWrite32 ((UINTN) Address, *(UINT32 *) Buffer);\r
- }\r
- break;\r
- case 8:\r
- if (Read) {\r
- *(UINT64 *) Buffer = MmioRead64 ((UINTN) Address);\r
- } else {\r
- MmioWrite64 ((UINTN) Address, *(UINT64 *) Buffer);\r
- }\r
- break;\r
- default:\r
- ASSERT (FALSE);\r
- break;\r
+ case 1:\r
+ if (Read) {\r
+ *(UINT8 *)Buffer = MmioRead8 ((UINTN)Address);\r
+ } else {\r
+ MmioWrite8 ((UINTN)Address, *(UINT8 *)Buffer);\r
+ }\r
+\r
+ break;\r
+ case 2:\r
+ if (Read) {\r
+ *(UINT16 *)Buffer = MmioRead16 ((UINTN)Address);\r
+ } else {\r
+ MmioWrite16 ((UINTN)Address, *(UINT16 *)Buffer);\r
+ }\r
+\r
+ break;\r
+ case 4:\r
+ if (Read) {\r
+ *(UINT32 *)Buffer = MmioRead32 ((UINTN)Address);\r
+ } else {\r
+ MmioWrite32 ((UINTN)Address, *(UINT32 *)Buffer);\r
+ }\r
+\r
+ break;\r
+ case 8:\r
+ if (Read) {\r
+ *(UINT64 *)Buffer = MmioRead64 ((UINTN)Address);\r
+ } else {\r
+ MmioWrite64 ((UINTN)Address, *(UINT64 *)Buffer);\r
+ }\r
+\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
}\r
}\r
**/\r
BOOLEAN\r
ShellMmLocateIoProtocol (\r
- IN SHELL_MM_ACCESS_TYPE AccessType,\r
- IN UINT64 Address,\r
- OUT EFI_CPU_IO2_PROTOCOL **CpuIo,\r
- OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **PciRootBridgeIo\r
+ IN SHELL_MM_ACCESS_TYPE AccessType,\r
+ IN UINT64 Address,\r
+ OUT EFI_CPU_IO2_PROTOCOL **CpuIo,\r
+ OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **PciRootBridgeIo\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINTN HandleCount;\r
- EFI_HANDLE *HandleBuffer;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Io;\r
- UINT32 Segment;\r
- UINT8 Bus;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
-\r
- Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **) CpuIo);\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINTN HandleCount;\r
+ EFI_HANDLE *HandleBuffer;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Io;\r
+ UINT32 Segment;\r
+ UINT8 Bus;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
+\r
+ Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)CpuIo);\r
if (EFI_ERROR (Status)) {\r
*CpuIo = NULL;\r
}\r
\r
*PciRootBridgeIo = NULL;\r
HandleBuffer = NULL;\r
- Status = gBS->LocateHandleBuffer (\r
- ByProtocol,\r
- &gEfiPciRootBridgeIoProtocolGuid,\r
- NULL,\r
- &HandleCount,\r
- &HandleBuffer\r
- );\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ &gEfiPciRootBridgeIoProtocolGuid,\r
+ NULL,\r
+ &HandleCount,\r
+ &HandleBuffer\r
+ );\r
if (EFI_ERROR (Status) || (HandleCount == 0) || (HandleBuffer == NULL)) {\r
return FALSE;\r
}\r
Segment = 0;\r
Bus = 0;\r
if ((AccessType == ShellMmPci) || (AccessType == ShellMmPciExpress)) {\r
- ShellMmDecodePciAddress ((BOOLEAN) (AccessType == ShellMmPci), Address, &Segment, &Bus, NULL, NULL, NULL);\r
+ ShellMmDecodePciAddress ((BOOLEAN)(AccessType == ShellMmPci), Address, &Segment, &Bus, NULL, NULL, NULL);\r
}\r
\r
//\r
Status = gBS->HandleProtocol (\r
HandleBuffer[Index],\r
&gEfiPciRootBridgeIoProtocolGuid,\r
- (VOID *) &Io\r
+ (VOID *)&Io\r
);\r
if (EFI_ERROR (Status)) {\r
continue;\r
\r
if ((((AccessType == ShellMmPci) || (AccessType == ShellMmPciExpress)) && (Io->SegmentNumber == Segment)) ||\r
((AccessType == ShellMmIo) || (AccessType == ShellMmMemoryMappedIo))\r
- ) {\r
- Status = Io->Configuration (Io, (VOID **) &Descriptors);\r
+ )\r
+ {\r
+ Status = Io->Configuration (Io, (VOID **)&Descriptors);\r
if (!EFI_ERROR (Status)) {\r
while (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
//\r
if ((Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) &&\r
((AccessType == ShellMmPci) || (AccessType == ShellMmPciExpress)) &&\r
((Bus >= Descriptors->AddrRangeMin) && (Bus <= Descriptors->AddrRangeMax))\r
- ) {\r
+ )\r
+ {\r
*PciRootBridgeIo = Io;\r
break;\r
\r
- //\r
- // Compare the address range for MMIO/IO access\r
- //\r
+ //\r
+ // Compare the address range for MMIO/IO access\r
+ //\r
} else if ((((Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_IO) && (AccessType == ShellMmIo)) ||\r
((Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) && (AccessType == ShellMmMemoryMappedIo))\r
) && ((Address >= Descriptors->AddrRangeMin) && (Address <= Descriptors->AddrRangeMax))\r
- ) {\r
+ )\r
+ {\r
*PciRootBridgeIo = Io;\r
break;\r
}\r
+\r
Descriptors++;\r
}\r
}\r
}\r
}\r
+\r
if (HandleBuffer != NULL) {\r
FreePool (HandleBuffer);\r
}\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
- EFI_CPU_IO2_PROTOCOL *CpuIo;\r
- UINT64 Address;\r
- UINT64 Value;\r
- SHELL_MM_ACCESS_TYPE AccessType;\r
- UINT64 Buffer;\r
- UINTN Index;\r
- UINTN Size;\r
- BOOLEAN Complete;\r
- CHAR16 *InputStr;\r
- BOOLEAN Interactive;\r
- LIST_ENTRY *Package;\r
- CHAR16 *ProblemParam;\r
- SHELL_STATUS ShellStatus;\r
- CONST CHAR16 *Temp;\r
- BOOLEAN HasPciRootBridgeIo;\r
-\r
- Value = 0;\r
- Address = 0;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
+ EFI_CPU_IO2_PROTOCOL *CpuIo;\r
+ UINT64 Address;\r
+ UINT64 Value;\r
+ SHELL_MM_ACCESS_TYPE AccessType;\r
+ UINT64 Buffer;\r
+ UINTN Index;\r
+ UINTN Size;\r
+ BOOLEAN Complete;\r
+ CHAR16 *InputStr;\r
+ BOOLEAN Interactive;\r
+ LIST_ENTRY *Package;\r
+ CHAR16 *ProblemParam;\r
+ SHELL_STATUS ShellStatus;\r
+ CONST CHAR16 *Temp;\r
+ BOOLEAN HasPciRootBridgeIo;\r
+\r
+ Value = 0;\r
+ Address = 0;\r
ShellStatus = SHELL_SUCCESS;\r
- InputStr = NULL;\r
- Size = 1;\r
- AccessType = ShellMmMemory;\r
+ InputStr = NULL;\r
+ Size = 1;\r
+ AccessType = ShellMmMemory;\r
\r
//\r
// Parse arguments\r
//\r
Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
if (EFI_ERROR (Status)) {\r
- if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
+ if ((Status == EFI_VOLUME_CORRUPTED) && (ProblemParam != NULL)) {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"mm", ProblemParam);\r
FreePool (ProblemParam);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"mm");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
- } else if (ShellCommandLineGetFlag (Package, L"-w") && ShellCommandLineGetValue (Package, L"-w") == NULL) {\r
+ } else if (ShellCommandLineGetFlag (Package, L"-w") && (ShellCommandLineGetValue (Package, L"-w") == NULL)) {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"mm", L"-w");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
} else {\r
if (ShellCommandLineGetFlag (Package, L"-mmio")) {\r
AccessType = ShellMmMemoryMappedIo;\r
- if (ShellCommandLineGetFlag (Package, L"-mem")\r
- || ShellCommandLineGetFlag (Package, L"-io")\r
- || ShellCommandLineGetFlag (Package, L"-pci")\r
- || ShellCommandLineGetFlag (Package, L"-pcie")\r
- ) {\r
+ if ( ShellCommandLineGetFlag (Package, L"-mem")\r
+ || ShellCommandLineGetFlag (Package, L"-io")\r
+ || ShellCommandLineGetFlag (Package, L"-pci")\r
+ || ShellCommandLineGetFlag (Package, L"-pcie")\r
+ )\r
+ {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"mm");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
} else if (ShellCommandLineGetFlag (Package, L"-mem")) {\r
AccessType = ShellMmMemory;\r
- if (ShellCommandLineGetFlag (Package, L"-io")\r
- || ShellCommandLineGetFlag (Package, L"-pci")\r
- || ShellCommandLineGetFlag (Package, L"-pcie")\r
- ) {\r
+ if ( ShellCommandLineGetFlag (Package, L"-io")\r
+ || ShellCommandLineGetFlag (Package, L"-pci")\r
+ || ShellCommandLineGetFlag (Package, L"-pcie")\r
+ )\r
+ {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"mm");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
} else if (ShellCommandLineGetFlag (Package, L"-io")) {\r
AccessType = ShellMmIo;\r
- if (ShellCommandLineGetFlag (Package, L"-pci")\r
- || ShellCommandLineGetFlag (Package, L"-pcie")\r
- ) {\r
+ if ( ShellCommandLineGetFlag (Package, L"-pci")\r
+ || ShellCommandLineGetFlag (Package, L"-pcie")\r
+ )\r
+ {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"mm");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
} else if (ShellCommandLineGetFlag (Package, L"-pci")) {\r
AccessType = ShellMmPci;\r
if (ShellCommandLineGetFlag (Package, L"-pcie")\r
- ) {\r
+ )\r
+ {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"mm");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
if (Temp != NULL) {\r
Size = ShellStrToUintn (Temp);\r
}\r
+\r
if ((Size != 1) && (Size != 2) && (Size != 4) && (Size != 8)) {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM_VAL), gShellDebug1HiiHandle, L"mm", Temp, L"-w");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
- Temp = ShellCommandLineGetRawValue (Package, 1);\r
+ Temp = ShellCommandLineGetRawValue (Package, 1);\r
Status = ShellConvertStringToUint64 (Temp, &Address, TRUE, FALSE);\r
if (EFI_ERROR (Status)) {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"mm", Temp);\r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
+\r
if (PciRootBridgeIo == NULL) {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_MM_PCIE_ADDRESS_RANGE), gShellDebug1HiiHandle, L"mm", Address);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
if (!gEfiShellProtocol->BatchIsActive ()) {\r
ShellPrintHiiEx (-1, -1, NULL, mShellMmAccessTypeStr[AccessType], gShellDebug1HiiHandle);\r
}\r
+\r
ShellMmAccess (AccessType, PciRootBridgeIo, CpuIo, TRUE, Address, Size, &Buffer);\r
\r
if (!gEfiShellProtocol->BatchIsActive ()) {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_MM_ADDRESS), gShellDebug1HiiHandle, Address);\r
}\r
+\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_MM_BUF), gShellDebug1HiiHandle, Size * 2, Buffer & mShellMmMaxNumber[Size]);\r
ShellPrintEx (-1, -1, L"\r\n");\r
goto Done;\r
FreePool (InputStr);\r
InputStr = NULL;\r
}\r
- ShellPromptForResponse (ShellPromptResponseTypeFreeform, NULL, (VOID**) &InputStr);\r
+\r
+ ShellPromptForResponse (ShellPromptResponseTypeFreeform, NULL, (VOID **)&InputStr);\r
\r
if (InputStr != NULL) {\r
//\r
// skip space characters\r
//\r
- for (Index = 0; InputStr[Index] == ' '; Index++);\r
+ for (Index = 0; InputStr[Index] == ' '; Index++) {\r
+ }\r
\r
if (InputStr[Index] != CHAR_NULL) {\r
if ((InputStr[Index] == '.') || (InputStr[Index] == 'q') || (InputStr[Index] == 'Q')) {\r
Complete = TRUE;\r
} else if (!EFI_ERROR (ShellConvertStringToUint64 (InputStr + Index, &Buffer, TRUE, TRUE)) &&\r
(Buffer <= mShellMmMaxNumber[Size])\r
- ) {\r
+ )\r
+ {\r
ShellMmAccess (AccessType, PciRootBridgeIo, CpuIo, FALSE, Address, Size, &Buffer);\r
} else {\r
ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_MM_ERROR), gShellDebug1HiiHandle, L"mm");\r
ShellPrintEx (-1, -1, L"\r\n");\r
} while (!Complete);\r
}\r
+\r
ASSERT (ShellStatus == SHELL_SUCCESS);\r
\r
Done:\r
if (InputStr != NULL) {\r
FreePool (InputStr);\r
}\r
+\r
if (Package != NULL) {\r
ShellCommandLineFreeVarList (Package);\r
}\r
+\r
return ShellStatus;\r
}\r
projects / mirror_edk2.git / blobdiff