/** @file\r
Main file for Pci shell Debug1 function.\r
\r
- Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
- Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2005 - 2021, Intel Corporation. All rights reserved.<BR>\r
+ (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <IndustryStandard/Acpi.h>\r
#include "Pci.h"\r
\r
-#define PCI_CLASS_STRING_LIMIT 54\r
//\r
// Printable strings for Pci class code\r
//\r
typedef struct {\r
- CHAR16 *BaseClass; // Pointer to the PCI base class string\r
- CHAR16 *SubClass; // Pointer to the PCI sub class string\r
- CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
+ CHAR16 *BaseClass; // Pointer to the PCI base class string\r
+ CHAR16 *SubClass; // Pointer to the PCI sub class string\r
+ CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
} PCI_CLASS_STRINGS;\r
\r
//\r
// class\r
//\r
typedef struct PCI_CLASS_ENTRY_TAG {\r
- UINT8 Code; // Class, subclass or I/F code\r
- CHAR16 *DescText; // Description string\r
- struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
+ UINT8 Code; // Class, subclass or I/F code\r
+ CHAR16 *DescText; // Description string\r
+ struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
} PCI_CLASS_ENTRY;\r
\r
//\r
// Declarations of entries which contain printable strings for class codes\r
// in PCI configuration space\r
//\r
-PCI_CLASS_ENTRY PCIBlankEntry[];\r
-PCI_CLASS_ENTRY PCISubClass_00[];\r
-PCI_CLASS_ENTRY PCISubClass_01[];\r
-PCI_CLASS_ENTRY PCISubClass_02[];\r
-PCI_CLASS_ENTRY PCISubClass_03[];\r
-PCI_CLASS_ENTRY PCISubClass_04[];\r
-PCI_CLASS_ENTRY PCISubClass_05[];\r
-PCI_CLASS_ENTRY PCISubClass_06[];\r
-PCI_CLASS_ENTRY PCISubClass_07[];\r
-PCI_CLASS_ENTRY PCISubClass_08[];\r
-PCI_CLASS_ENTRY PCISubClass_09[];\r
-PCI_CLASS_ENTRY PCISubClass_0a[];\r
-PCI_CLASS_ENTRY PCISubClass_0b[];\r
-PCI_CLASS_ENTRY PCISubClass_0c[];\r
-PCI_CLASS_ENTRY PCISubClass_0d[];\r
-PCI_CLASS_ENTRY PCISubClass_0e[];\r
-PCI_CLASS_ENTRY PCISubClass_0f[];\r
-PCI_CLASS_ENTRY PCISubClass_10[];\r
-PCI_CLASS_ENTRY PCISubClass_11[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
-PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
+PCI_CLASS_ENTRY PCIBlankEntry[];\r
+PCI_CLASS_ENTRY PCISubClass_00[];\r
+PCI_CLASS_ENTRY PCISubClass_01[];\r
+PCI_CLASS_ENTRY PCISubClass_02[];\r
+PCI_CLASS_ENTRY PCISubClass_03[];\r
+PCI_CLASS_ENTRY PCISubClass_04[];\r
+PCI_CLASS_ENTRY PCISubClass_05[];\r
+PCI_CLASS_ENTRY PCISubClass_06[];\r
+PCI_CLASS_ENTRY PCISubClass_07[];\r
+PCI_CLASS_ENTRY PCISubClass_08[];\r
+PCI_CLASS_ENTRY PCISubClass_09[];\r
+PCI_CLASS_ENTRY PCISubClass_0a[];\r
+PCI_CLASS_ENTRY PCISubClass_0b[];\r
+PCI_CLASS_ENTRY PCISubClass_0c[];\r
+PCI_CLASS_ENTRY PCISubClass_0d[];\r
+PCI_CLASS_ENTRY PCISubClass_0e[];\r
+PCI_CLASS_ENTRY PCISubClass_0f[];\r
+PCI_CLASS_ENTRY PCISubClass_10[];\r
+PCI_CLASS_ENTRY PCISubClass_11[];\r
+PCI_CLASS_ENTRY PCISubClass_12[];\r
+PCI_CLASS_ENTRY PCISubClass_13[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0100[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0105[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0106[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0107[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0108[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0109[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0609[];\r
+PCI_CLASS_ENTRY PCIPIFClass_060b[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
\r
//\r
// Base class strings entries\r
//\r
-PCI_CLASS_ENTRY gClassStringList[] = {\r
+PCI_CLASS_ENTRY gClassStringList[] = {\r
{\r
0x00,\r
L"Pre 2.0 device",\r
L"Data Acquisition & Signal Processing Controllers",\r
PCISubClass_11\r
},\r
+ {\r
+ 0x12,\r
+ L"Processing Accelerators",\r
+ PCISubClass_12\r
+ },\r
+ {\r
+ 0x13,\r
+ L"Non-Essential Instrumentation",\r
+ PCISubClass_13\r
+ },\r
{\r
0xff,\r
L"Device does not fit in any defined classes",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
//\r
// Subclass strings entries\r
//\r
-PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
+PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
{\r
0x00,\r
L"",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_00[] = {\r
+PCI_CLASS_ENTRY PCISubClass_00[] = {\r
{\r
0x00,\r
L"All devices other than VGA",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_01[] = {\r
+PCI_CLASS_ENTRY PCISubClass_01[] = {\r
{\r
0x00,\r
- L"SCSI controller",\r
- PCIBlankEntry\r
+ L"SCSI",\r
+ PCIPIFClass_0100\r
},\r
{\r
0x01,\r
L"RAID controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x05,\r
+ L"ATA controller with ADMA interface",\r
+ PCIPIFClass_0105\r
+ },\r
+ {\r
+ 0x06,\r
+ L"Serial ATA controller",\r
+ PCIPIFClass_0106\r
+ },\r
+ {\r
+ 0x07,\r
+ L"Serial Attached SCSI (SAS) controller ",\r
+ PCIPIFClass_0107\r
+ },\r
+ {\r
+ 0x08,\r
+ L"Non-volatile memory subsystem",\r
+ PCIPIFClass_0108\r
+ },\r
+ {\r
+ 0x09,\r
+ L"Universal Flash Storage (UFS) controller ",\r
+ PCIPIFClass_0109\r
+ },\r
{\r
0x80,\r
L"Other mass storage controller",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_02[] = {\r
+PCI_CLASS_ENTRY PCISubClass_02[] = {\r
{\r
0x00,\r
L"Ethernet controller",\r
L"ISDN controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x05,\r
+ L"WorldFip controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x06,\r
+ L"PICMG 2.14 Multi Computing",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x07,\r
+ L"InfiniBand controller",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other network controller",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_03[] = {\r
+PCI_CLASS_ENTRY PCISubClass_03[] = {\r
{\r
0x00,\r
L"VGA/8514 controller",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */PCIBlankEntry\r
+ /* null string ends the list */ PCIBlankEntry\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_04[] = {\r
+PCI_CLASS_ENTRY PCISubClass_04[] = {\r
{\r
0x00,\r
L"Video device",\r
L"Computer Telephony device",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x03,\r
+ L"Mixed mode device",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other multimedia device",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_05[] = {\r
+PCI_CLASS_ENTRY PCISubClass_05[] = {\r
{\r
0x00,\r
L"RAM memory controller",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_06[] = {\r
+PCI_CLASS_ENTRY PCISubClass_06[] = {\r
{\r
0x00,\r
L"Host/PCI bridge",\r
L"RACEway bridge",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x09,\r
+ L"Semi-transparent PCI-to-PCI bridge",\r
+ PCIPIFClass_0609\r
+ },\r
+ {\r
+ 0x0A,\r
+ L"InfiniBand-to-PCI host bridge",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x0B,\r
+ L"Advanced Switching to PCI host bridge",\r
+ PCIPIFClass_060b\r
+ },\r
{\r
0x80,\r
L"Other bridge type",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_07[] = {\r
+PCI_CLASS_ENTRY PCISubClass_07[] = {\r
{\r
0x00,\r
L"Serial controller",\r
L"Modem",\r
PCIPIFClass_0703\r
},\r
+ {\r
+ 0x04,\r
+ L"GPIB (IEEE 488.1/2) controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x05,\r
+ L"Smart Card",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other communication device",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_08[] = {\r
+PCI_CLASS_ENTRY PCISubClass_08[] = {\r
{\r
0x00,\r
L"PIC",\r
L"Generic PCI Hot-Plug controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x05,\r
+ L"SD Host controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x06,\r
+ L"IOMMU",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x07,\r
+ L"Root Complex Event Collector",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other system peripheral",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_09[] = {\r
+PCI_CLASS_ENTRY PCISubClass_09[] = {\r
{\r
0x00,\r
L"Keyboard controller",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
+PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
{\r
0x00,\r
L"Generic docking station",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
+PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
{\r
0x00,\r
L"386",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
+PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
{\r
0x00,\r
- L"Firewire(IEEE 1394)",\r
- PCIPIFClass_0c03\r
+ L"IEEE 1394",\r
+ PCIPIFClass_0c00\r
},\r
{\r
0x01,\r
{\r
0x03,\r
L"USB",\r
- PCIPIFClass_0c00\r
+ PCIPIFClass_0c03\r
},\r
{\r
0x04,\r
L"System Management Bus",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x06,\r
+ L"InfiniBand",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x07,\r
+ L"IPMI",\r
+ PCIPIFClass_0c07\r
+ },\r
+ {\r
+ 0x08,\r
+ L"SERCOS Interface Standard (IEC 61491)",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x09,\r
+ L"CANbus",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other bus type",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
+PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
{\r
0x00,\r
L"iRDA compatible controller",\r
},\r
{\r
0x01,\r
- L"Consumer IR controller",\r
- PCIBlankEntry\r
+ L"",\r
+ PCIPIFClass_0d01\r
},\r
{\r
0x10,\r
L"RF controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x11,\r
+ L"Bluetooth",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x12,\r
+ L"Broadband",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x20,\r
+ L"Ethernet (802.11a - 5 GHz)",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x21,\r
+ L"Ethernet (802.11b - 2.4 GHz)",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other type of wireless controller",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
+PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
{\r
0x00,\r
L"I2O Architecture",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
+PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
{\r
- 0x00,\r
+ 0x01,\r
L"TV",\r
PCIBlankEntry\r
},\r
{\r
- 0x01,\r
+ 0x02,\r
L"Audio",\r
PCIBlankEntry\r
},\r
{\r
- 0x02,\r
+ 0x03,\r
L"Voice",\r
PCIBlankEntry\r
},\r
{\r
- 0x03,\r
+ 0x04,\r
L"Data",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x80,\r
+ L"Other satellite communication controller",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_10[] = {\r
+PCI_CLASS_ENTRY PCISubClass_10[] = {\r
{\r
0x00,\r
L"Network & computing Encrypt/Decrypt",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCISubClass_11[] = {\r
+PCI_CLASS_ENTRY PCISubClass_11[] = {\r
{\r
0x00,\r
L"DPIO modules",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x01,\r
+ L"Performance Counters",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x10,\r
+ L"Communications synchronization plus time and frequency test/measurement ",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x20,\r
+ L"Management card",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other DAQ & SP controllers",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCISubClass_12[] = {\r
+ {\r
+ 0x00,\r
+ L"Processing Accelerator",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCISubClass_13[] = {\r
+ {\r
+ 0x00,\r
+ L"Non-Essential Instrumentation Function",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
//\r
// Programming Interface entries\r
//\r
-PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r
+ {\r
+ 0x00,\r
+ L"SCSI controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x11,\r
+ L"SCSI storage device SOP using PQI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x12,\r
+ L"SCSI controller SOP using PQI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x13,\r
+ L"SCSI storage device and controller SOP using PQI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x21,\r
+ L"SCSI storage device SOP using NVMe",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
{\r
0x00,\r
L"",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r
{\r
- 0x00,\r
- L"VGA compatible",\r
+ 0x20,\r
+ L"Single stepping",\r
PCIBlankEntry\r
},\r
{\r
- 0x01,\r
- L"8514 compatible",\r
+ 0x30,\r
+ L"Continuous operation",\r
PCIBlankEntry\r
},\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r
{\r
0x00,\r
L"",\r
},\r
{\r
0x01,\r
- L"Subtractive decode",\r
+ L"AHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"Serial Storage Bus",\r
PCIBlankEntry\r
},\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r
{\r
0x00,\r
- L"Generic XT-compatible",\r
+ L"",\r
PCIBlankEntry\r
},\r
{\r
0x01,\r
- L"16450-compatible",\r
- PCIBlankEntry\r
- },\r
- {\r
- 0x02,\r
- L"16550-compatible",\r
+ L"Obsolete",\r
PCIBlankEntry\r
},\r
{\r
- 0x03,\r
- L"16650-compatible",\r
- PCIBlankEntry\r
- },\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r
{\r
- 0x04,\r
- L"16750-compatible",\r
+ 0x00,\r
+ L"",\r
PCIBlankEntry\r
},\r
{\r
- 0x05,\r
- L"16850-compatible",\r
+ 0x01,\r
+ L"NVMHCI",\r
PCIBlankEntry\r
},\r
{\r
- 0x06,\r
- L"16950-compatible",\r
+ 0x02,\r
+ L"NVM Express",\r
PCIBlankEntry\r
},\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r
{\r
0x00,\r
L"",\r
},\r
{\r
0x01,\r
- L"Bi-directional",\r
+ L"UFSHCI",\r
PCIBlankEntry\r
},\r
{\r
- 0x02,\r
- L"ECP 1.X-compliant",\r
- PCIBlankEntry\r
- },\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
{\r
- 0x03,\r
- L"IEEE 1284",\r
+ 0x00,\r
+ L"VGA compatible",\r
PCIBlankEntry\r
},\r
{\r
- 0xfe,\r
- L"IEEE 1284 target (not a controller)",\r
+ 0x01,\r
+ L"8514 compatible",\r
PCIBlankEntry\r
},\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
{\r
0x00,\r
- L"Generic",\r
+ L"",\r
PCIBlankEntry\r
},\r
{\r
0x01,\r
- L"Hayes-compatible 16450",\r
+ L"Subtractive decode",\r
PCIBlankEntry\r
},\r
{\r
- 0x02,\r
- L"Hayes-compatible 16550",\r
- PCIBlankEntry\r
- },\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r
{\r
- 0x03,\r
- L"Hayes-compatible 16650",\r
+ 0x40,\r
+ L"Primary PCI bus side facing the system host processor",\r
PCIBlankEntry\r
},\r
{\r
- 0x04,\r
- L"Hayes-compatible 16750",\r
+ 0x80,\r
+ L"Secondary PCI bus side facing the system host processor",\r
PCIBlankEntry\r
},\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r
{\r
0x00,\r
- L"Generic 8259",\r
+ L"Custom",\r
PCIBlankEntry\r
},\r
{\r
0x01,\r
- L"ISA",\r
- PCIBlankEntry\r
- },\r
- {\r
- 0x02,\r
- L"EISA",\r
+ L"ASI-SIG Defined Portal",\r
PCIBlankEntry\r
},\r
{\r
- 0x10,\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
+ {\r
+ 0x00,\r
+ L"Generic XT-compatible",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"16450-compatible",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"16550-compatible",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x03,\r
+ L"16650-compatible",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x04,\r
+ L"16750-compatible",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x05,\r
+ L"16850-compatible",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x06,\r
+ L"16950-compatible",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"Bi-directional",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"ECP 1.X-compliant",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x03,\r
+ L"IEEE 1284",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0xfe,\r
+ L"IEEE 1284 target (not a controller)",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
+ {\r
+ 0x00,\r
+ L"Generic",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"Hayes-compatible 16450",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"Hayes-compatible 16550",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x03,\r
+ L"Hayes-compatible 16650",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x04,\r
+ L"Hayes-compatible 16750",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
+ {\r
+ 0x00,\r
+ L"Generic 8259",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"ISA",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"EISA",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x10,\r
L"IO APIC",\r
PCIBlankEntry\r
},\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
{\r
0x00,\r
L"Generic 8237",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
{\r
0x00,\r
L"Generic 8254",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
{\r
0x00,\r
L"Generic",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
{\r
0x00,\r
L"Generic",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x10,\r
+ L"Using 1394 OpenHCI spec",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
{\r
0x00,\r
- L"Universal Host Controller spec",\r
+ L"UHCI",\r
PCIBlankEntry\r
},\r
{\r
0x10,\r
- L"Open Host Controller spec",\r
+ L"OHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x20,\r
+ L"EHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x30,\r
+ L"xHCI",\r
PCIBlankEntry\r
},\r
{\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r
{\r
0x00,\r
- L"",\r
+ L"SMIC",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"Keyboard Controller Style",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"Block Transfer",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */ NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r
+ {\r
+ 0x00,\r
+ L"Consumer IR controller",\r
PCIBlankEntry\r
},\r
{\r
0x10,\r
- L"Using 1394 OpenHCI spec",\r
+ L"UWB Radio controller",\r
PCIBlankEntry\r
},\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
{\r
0x00,\r
L"Message FIFO at offset 40h",\r
{\r
0x00,\r
NULL,\r
- /* null string ends the list */NULL\r
+ /* null string ends the list */ NULL\r
}\r
};\r
\r
-\r
/**\r
Generates printable Unicode strings that represent PCI device class,\r
subclass and programmed I/F based on a value passed to the function.\r
**/\r
VOID\r
PciGetClassStrings (\r
- IN UINT32 ClassCode,\r
- IN OUT PCI_CLASS_STRINGS *ClassStrings\r
+ IN UINT32 ClassCode,\r
+ IN OUT PCI_CLASS_STRINGS *ClassStrings\r
)\r
{\r
- INTN Index;\r
- UINT8 Code;\r
- PCI_CLASS_ENTRY *CurrentClass;\r
+ INTN Index;\r
+ UINT8 Code;\r
+ PCI_CLASS_ENTRY *CurrentClass;\r
\r
//\r
// Assume no strings found\r
ClassStrings->PIFClass = L"UNDEFINED";\r
\r
CurrentClass = gClassStringList;\r
- Code = (UINT8) (ClassCode >> 16);\r
- Index = 0;\r
+ Code = (UINT8)(ClassCode >> 16);\r
+ Index = 0;\r
\r
//\r
// Go through all entries of the base class, until the entry with a matching\r
//\r
while (Code != CurrentClass[Index].Code) {\r
if (NULL == CurrentClass[Index].DescText) {\r
- return ;\r
+ return;\r
}\r
\r
Index++;\r
}\r
+\r
//\r
// A base class was found. Assign description, and check if this class has\r
// sub-class defined. If sub-class defined, no more action is needed,\r
//\r
ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
if (NULL == CurrentClass[Index].LowerLevelClass) {\r
- return ;\r
+ return;\r
}\r
+\r
//\r
// find Subclass entry\r
//\r
- CurrentClass = CurrentClass[Index].LowerLevelClass;\r
- Code = (UINT8) (ClassCode >> 8);\r
- Index = 0;\r
+ CurrentClass = CurrentClass[Index].LowerLevelClass;\r
+ Code = (UINT8)(ClassCode >> 8);\r
+ Index = 0;\r
\r
//\r
// Go through all entries of the sub-class, until the entry with a matching\r
//\r
while (Code != CurrentClass[Index].Code) {\r
if (NULL == CurrentClass[Index].DescText) {\r
- return ;\r
+ return;\r
}\r
\r
Index++;\r
}\r
+\r
//\r
// A class was found for the sub-class code. Assign description, and check if\r
// this sub-class has programming interface defined. If no, no more action is\r
//\r
ClassStrings->SubClass = CurrentClass[Index].DescText;\r
if (NULL == CurrentClass[Index].LowerLevelClass) {\r
- return ;\r
+ return;\r
}\r
+\r
//\r
// Find programming interface entry\r
//\r
- CurrentClass = CurrentClass[Index].LowerLevelClass;\r
- Code = (UINT8) ClassCode;\r
- Index = 0;\r
+ CurrentClass = CurrentClass[Index].LowerLevelClass;\r
+ Code = (UINT8)ClassCode;\r
+ Index = 0;\r
\r
//\r
// Go through all entries of the I/F entries, until the entry with a\r
//\r
while (Code != CurrentClass[Index].Code) {\r
if (NULL == CurrentClass[Index].DescText) {\r
- return ;\r
+ return;\r
}\r
\r
Index++;\r
}\r
+\r
//\r
// A class was found for the I/F code. Assign description, done!\r
//\r
ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
- return ;\r
+ return;\r
}\r
\r
/**\r
Print strings that represent PCI device class, subclass and programmed I/F.\r
\r
@param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
- configuation space.\r
+ configuration space.\r
@param[in] IncludePIF If the printed string should include the programming I/F part\r
**/\r
VOID\r
PciPrintClassCode (\r
- IN UINT8 *ClassCodePtr,\r
- IN BOOLEAN IncludePIF\r
+ IN UINT8 *ClassCodePtr,\r
+ IN BOOLEAN IncludePIF\r
)\r
{\r
- UINT32 ClassCode;\r
- PCI_CLASS_STRINGS ClassStrings;\r
+ UINT32 ClassCode;\r
+ PCI_CLASS_STRINGS ClassStrings;\r
\r
- ClassCode = 0;\r
- ClassCode |= ClassCodePtr[0];\r
- ClassCode |= (ClassCodePtr[1] << 8);\r
- ClassCode |= (ClassCodePtr[2] << 16);\r
+ ClassCode = 0;\r
+ ClassCode |= (UINT32)ClassCodePtr[0];\r
+ ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r
+ ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r
\r
//\r
// Get name from class code\r
//\r
// Print base class, sub class, and programming inferface name\r
//\r
- ShellPrintEx (-1, -1, L"%s - %s - %s",\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
+ L"%s - %s - %s",\r
ClassStrings.BaseClass,\r
ClassStrings.SubClass,\r
ClassStrings.PIFClass\r
- );\r
-\r
+ );\r
} else {\r
//\r
// Only print base class and sub class name\r
//\r
- ShellPrintEx (-1, -1, L"%s - %s",\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
+ L"%s - %s",\r
ClassStrings.BaseClass,\r
ClassStrings.SubClass\r
- );\r
+ );\r
}\r
}\r
\r
**/\r
EFI_STATUS\r
PciFindProtocolInterface (\r
- IN EFI_HANDLE *HandleBuf,\r
- IN UINTN HandleCount,\r
- IN UINT16 Segment,\r
- IN UINT16 Bus,\r
- OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
+ IN EFI_HANDLE *HandleBuf,\r
+ IN UINTN HandleCount,\r
+ IN UINT16 Segment,\r
+ IN UINT16 Bus,\r
+ OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
PciGetProtocolAndResource (\r
- IN EFI_HANDLE Handle,\r
- OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
- OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
+ IN EFI_HANDLE Handle,\r
+ OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
+ OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
);\r
\r
/**\r
@param[in] ConfigSpace Data in PCI configuration space.\r
@param[in] Address Address used to access configuration space of this PCI device.\r
@param[in] IoDev Handle used to access configuration space of PCI device.\r
-\r
- @retval EFI_SUCCESS The command completed successfully.\r
**/\r
-EFI_STATUS\r
-PciExplainData (\r
- IN PCI_CONFIG_SPACE *ConfigSpace,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+VOID\r
+PciExplainPci (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
- IN PCI_DEVICE_HEADER *Device,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
- IN PCI_BRIDGE_HEADER *Bridge,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
PciExplainBar (\r
- IN UINT32 *Bar,\r
- IN UINT16 *Command,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN OUT UINTN *Index\r
+ IN UINT32 *Bar,\r
+ IN UINT16 *Command,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
+ IN OUT UINTN *Index\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
- IN PCI_CARDBUS_HEADER *CardBus,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
PciExplainStatus (\r
- IN UINT16 *Status,\r
- IN BOOLEAN MainStatus,\r
- IN PCI_HEADER_TYPE HeaderType\r
+ IN UINT16 *Status,\r
+ IN BOOLEAN MainStatus,\r
+ IN PCI_HEADER_TYPE HeaderType\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
PciExplainCommand (\r
- IN UINT16 *Command\r
+ IN UINT16 *Command\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
PciExplainBridgeControl (\r
- IN UINT16 *BridgeControl,\r
- IN PCI_HEADER_TYPE HeaderType\r
+ IN UINT16 *BridgeControl,\r
+ IN PCI_HEADER_TYPE HeaderType\r
);\r
\r
/**\r
- Print each capability structure.\r
+ Locate capability register block per capability ID.\r
\r
- @param[in] IoDev The pointer to the deivce.\r
- @param[in] Address The address to start at.\r
- @param[in] CapPtr The offset from the address.\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] CapabilityId The capability ID.\r
\r
- @retval EFI_SUCCESS The operation was successful.\r
+ @return The offset of the register block per capability ID.\r
**/\r
-EFI_STATUS\r
-PciExplainCapabilityStruct (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapPtr\r
+UINT8\r
+LocatePciCapability (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT8 CapabilityId\r
);\r
\r
/**\r
Display Pcie device structure.\r
\r
- @param[in] IoDev The pointer to the root pci protocol.\r
- @param[in] Address The Address to start at.\r
- @param[in] CapabilityPtr The offset from the address to start.\r
+ @param[in] PciExpressCap PCI Express capability buffer.\r
+ @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r
+ @param[in] ExtendedConfigSize PCI Express extended configuration size.\r
+ @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r
**/\r
-EFI_STATUS\r
+VOID\r
PciExplainPciExpress (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapabilityPtr\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r
+ IN UINT8 *ExtendedConfigSpace,\r
+ IN UINTN ExtendedConfigSize,\r
+ IN CONST UINT16 ExtendedCapability\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
-typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
+typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
+ );\r
\r
typedef enum {\r
FieldWidthUINT8,\r
PcieExplainTypeMax\r
} PCIE_EXPLAIN_TYPE;\r
\r
-typedef struct\r
-{\r
- UINT16 Token;\r
- UINTN Offset;\r
- PCIE_CAPREG_FIELD_WIDTH Width;\r
- PCIE_EXPLAIN_FUNCTION Func;\r
- PCIE_EXPLAIN_TYPE Type;\r
+typedef struct {\r
+ UINT16 Token;\r
+ UINTN Offset;\r
+ PCIE_CAPREG_FIELD_WIDTH Width;\r
+ PCIE_EXPLAIN_FUNCTION Func;\r
+ PCIE_EXPLAIN_TYPE Type;\r
} PCIE_EXPLAIN_STRUCT;\r
\r
-PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
+PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
{\r
STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
0x00,\r
//\r
// Global Variables\r
//\r
-PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
-STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
- {L"-s", TypeValue},\r
- {L"-i", TypeFlag},\r
- {NULL, TypeMax}\r
- };\r
-\r
-CHAR16 *DevicePortTypeTable[] = {\r
+PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
+STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
+ { L"-s", TypeValue },\r
+ { L"-i", TypeFlag },\r
+ { L"-ec", TypeValue },\r
+ { NULL, TypeMax }\r
+};\r
+\r
+CHAR16 *DevicePortTypeTable[] = {\r
L"PCI Express Endpoint",\r
L"Legacy PCI Express Endpoint",\r
L"Unknown Type",\r
L"Root Complex Event Collector"\r
};\r
\r
-CHAR16 *L0sLatencyStrTable[] = {\r
+CHAR16 *L0sLatencyStrTable[] = {\r
L"Less than 64ns",\r
L"64ns to less than 128ns",\r
L"128ns to less than 256ns",\r
L"More than 4us"\r
};\r
\r
-CHAR16 *L1LatencyStrTable[] = {\r
+CHAR16 *L1LatencyStrTable[] = {\r
L"Less than 1us",\r
L"1us to less than 2us",\r
L"2us to less than 4us",\r
L"More than 64us"\r
};\r
\r
-CHAR16 *ASPMCtrlStrTable[] = {\r
+CHAR16 *ASPMCtrlStrTable[] = {\r
L"Disabled",\r
L"L0s Entry Enabled",\r
L"L1 Entry Enabled",\r
L"L0s and L1 Entry Enabled"\r
};\r
\r
-CHAR16 *SlotPwrLmtScaleTable[] = {\r
+CHAR16 *SlotPwrLmtScaleTable[] = {\r
L"1.0x",\r
L"0.1x",\r
L"0.01x",\r
L"0.001x"\r
};\r
\r
-CHAR16 *IndicatorTable[] = {\r
+CHAR16 *IndicatorTable[] = {\r
L"Reserved",\r
L"On",\r
L"Blink",\r
L"Off"\r
};\r
\r
-\r
/**\r
Function for 'pci' command.\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- UINT16 Segment;\r
- UINT16 Bus;\r
- UINT16 Device;\r
- UINT16 Func;\r
- UINT64 Address;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
- EFI_STATUS Status;\r
- PCI_COMMON_HEADER PciHeader;\r
- PCI_CONFIG_SPACE ConfigSpace;\r
- UINTN ScreenCount;\r
- UINTN TempColumn;\r
- UINTN ScreenSize;\r
- BOOLEAN ExplainData;\r
- UINTN Index;\r
- UINTN SizeOfHeader;\r
- BOOLEAN PrintTitle;\r
- UINTN HandleBufSize;\r
- EFI_HANDLE *HandleBuf;\r
- UINTN HandleCount;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
- UINT16 MinBus;\r
- UINT16 MaxBus;\r
- BOOLEAN IsEnd;\r
- LIST_ENTRY *Package;\r
- CHAR16 *ProblemParam;\r
- SHELL_STATUS ShellStatus;\r
- CONST CHAR16 *Temp;\r
- UINT64 RetVal;\r
-\r
- ShellStatus = SHELL_SUCCESS;\r
- Status = EFI_SUCCESS;\r
- Address = 0;\r
- IoDev = NULL;\r
- HandleBuf = NULL;\r
- Package = NULL;\r
+ UINT16 Segment;\r
+ UINT16 Bus;\r
+ UINT16 Device;\r
+ UINT16 Func;\r
+ UINT64 Address;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
+ EFI_STATUS Status;\r
+ PCI_DEVICE_INDEPENDENT_REGION PciHeader;\r
+ PCI_CONFIG_SPACE ConfigSpace;\r
+ UINTN ScreenCount;\r
+ UINTN TempColumn;\r
+ UINTN ScreenSize;\r
+ BOOLEAN ExplainData;\r
+ UINTN Index;\r
+ UINTN SizeOfHeader;\r
+ BOOLEAN PrintTitle;\r
+ UINTN HandleBufSize;\r
+ EFI_HANDLE *HandleBuf;\r
+ UINTN HandleCount;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
+ UINT16 MinBus;\r
+ UINT16 MaxBus;\r
+ BOOLEAN IsEnd;\r
+ LIST_ENTRY *Package;\r
+ CHAR16 *ProblemParam;\r
+ SHELL_STATUS ShellStatus;\r
+ CONST CHAR16 *Temp;\r
+ UINT64 RetVal;\r
+ UINT16 ExtendedCapability;\r
+ UINT8 PcieCapabilityPtr;\r
+ UINT8 *ExtendedConfigSpace;\r
+ UINTN ExtendedConfigSize;\r
+\r
+ ShellStatus = SHELL_SUCCESS;\r
+ Status = EFI_SUCCESS;\r
+ Address = 0;\r
+ IoDev = NULL;\r
+ HandleBuf = NULL;\r
+ Package = NULL;\r
\r
//\r
// initialize the shell lib (we must be in non-auto-init...)\r
//\r
- Status = ShellInitialize();\r
- ASSERT_EFI_ERROR(Status);\r
+ Status = ShellInitialize ();\r
+ ASSERT_EFI_ERROR (Status);\r
\r
- Status = CommandInit();\r
- ASSERT_EFI_ERROR(Status);\r
+ Status = CommandInit ();\r
+ ASSERT_EFI_ERROR (Status);\r
\r
//\r
// parse the command line\r
//\r
Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
- if (EFI_ERROR(Status)) {\r
- if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
- FreePool(ProblemParam);\r
+ if (EFI_ERROR (Status)) {\r
+ if ((Status == EFI_VOLUME_CORRUPTED) && (ProblemParam != NULL)) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam);\r
+ FreePool (ProblemParam);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
} else {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
} else {\r
+ if (ShellCommandLineGetCount (Package) == 2) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci");\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
\r
- if (ShellCommandLineGetCount(Package) == 2) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
+ if (ShellCommandLineGetCount (Package) > 4) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
- if (ShellCommandLineGetCount(Package) > 4) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
+ if (ShellCommandLineGetFlag (Package, L"-ec") && (ShellCommandLineGetValue (Package, L"-ec") == NULL)) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-ec");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
- if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
+\r
+ if (ShellCommandLineGetFlag (Package, L"-s") && (ShellCommandLineGetValue (Package, L"-s") == NULL)) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
+\r
//\r
// Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
// call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
// space for handles and call it again.\r
//\r
HandleBufSize = sizeof (EFI_HANDLE);\r
- HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
+ HandleBuf = (EFI_HANDLE *)AllocateZeroPool (HandleBufSize);\r
if (HandleBuf == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_OUT_OF_RESOURCES;\r
goto Done;\r
}\r
\r
Status = gBS->LocateHandle (\r
- ByProtocol,\r
- &gEfiPciRootBridgeIoProtocolGuid,\r
- NULL,\r
- &HandleBufSize,\r
- HandleBuf\r
- );\r
+ ByProtocol,\r
+ &gEfiPciRootBridgeIoProtocolGuid,\r
+ NULL,\r
+ &HandleBufSize,\r
+ HandleBuf\r
+ );\r
\r
if (Status == EFI_BUFFER_TOO_SMALL) {\r
HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
if (HandleBuf == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_OUT_OF_RESOURCES;\r
goto Done;\r
}\r
\r
Status = gBS->LocateHandle (\r
- ByProtocol,\r
- &gEfiPciRootBridgeIoProtocolGuid,\r
- NULL,\r
- &HandleBufSize,\r
- HandleBuf\r
- );\r
+ ByProtocol,\r
+ &gEfiPciRootBridgeIoProtocolGuid,\r
+ NULL,\r
+ &HandleBufSize,\r
+ HandleBuf\r
+ );\r
}\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
//\r
// Argument Count == 1(no other argument): enumerate all pci functions\r
//\r
- if (ShellCommandLineGetCount(Package) == 1) {\r
+ if (ShellCommandLineGetCount (Package) == 1) {\r
gST->ConOut->QueryMode (\r
- gST->ConOut,\r
- gST->ConOut->Mode->Mode,\r
- &TempColumn,\r
- &ScreenSize\r
- );\r
+ gST->ConOut,\r
+ gST->ConOut->Mode->Mode,\r
+ &TempColumn,\r
+ &ScreenSize\r
+ );\r
\r
ScreenCount = 0;\r
ScreenSize -= 4;\r
//\r
for (Index = 0; Index < HandleCount; Index++) {\r
Status = PciGetProtocolAndResource (\r
- HandleBuf[Index],\r
- &IoDev,\r
- &Descriptors\r
- );\r
+ HandleBuf[Index],\r
+ &IoDev,\r
+ &Descriptors\r
+ );\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
+\r
//\r
// No document say it's impossible for a RootBridgeIo protocol handle\r
// to have more than one address space descriptors, so find out every\r
Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
ShellStatus = SHELL_ABORTED;\r
goto Done;\r
}\r
- Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
+\r
+ Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
IoDev->Pci.Read (\r
- IoDev,\r
- EfiPciWidthUint16,\r
- Address,\r
- 1,\r
- &PciHeader.VendorId\r
- );\r
+ IoDev,\r
+ EfiPciWidthUint16,\r
+ Address,\r
+ 1,\r
+ &PciHeader.VendorId\r
+ );\r
\r
//\r
// If VendorId = 0xffff, there does not exist a device at this\r
// will be no more functions in the same device, so we can break\r
// loop to deal with the next device.\r
//\r
- if (PciHeader.VendorId == 0xffff && Func == 0) {\r
+ if ((PciHeader.VendorId == 0xffff) && (Func == 0)) {\r
break;\r
}\r
\r
if (PciHeader.VendorId != 0xffff) {\r
-\r
if (PrintTitle) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
PrintTitle = FALSE;\r
}\r
\r
IoDev->Pci.Read (\r
- IoDev,\r
- EfiPciWidthUint32,\r
- Address,\r
- sizeof (PciHeader) / sizeof (UINT32),\r
- &PciHeader\r
- );\r
-\r
- ShellPrintHiiEx(\r
- -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
+ IoDev,\r
+ EfiPciWidthUint32,\r
+ Address,\r
+ sizeof (PciHeader) / sizeof (UINT32),\r
+ &PciHeader\r
+ );\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_LINE_P1),\r
+ gShellDebug1HiiHandle,\r
IoDev->SegmentNumber,\r
Bus,\r
Device,\r
Func\r
- );\r
+ );\r
\r
PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
- ShellPrintHiiEx(\r
- -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_LINE_P2),\r
+ gShellDebug1HiiHandle,\r
PciHeader.VendorId,\r
PciHeader.DeviceId,\r
PciHeader.ClassCode[0]\r
- );\r
+ );\r
\r
ScreenCount += 2;\r
- if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
+ if ((ScreenCount >= ScreenSize) && (ScreenSize != 0)) {\r
//\r
// If ScreenSize == 0 we have the console redirected so don't\r
// block updates\r
//\r
ScreenCount = 0;\r
}\r
+\r
//\r
// If this is not a multi-function device, we can leave the loop\r
// to deal with the next device.\r
//\r
- if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
+ if ((Func == 0) && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
break;\r
}\r
}\r
}\r
}\r
}\r
+\r
//\r
// If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
// we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
goto Done;\r
}\r
\r
- ExplainData = FALSE;\r
- Segment = 0;\r
- Bus = 0;\r
- Device = 0;\r
- Func = 0;\r
- if (ShellCommandLineGetFlag(Package, L"-i")) {\r
+ ExplainData = FALSE;\r
+ Segment = 0;\r
+ Bus = 0;\r
+ Device = 0;\r
+ Func = 0;\r
+ ExtendedCapability = 0xFFFF;\r
+ if (ShellCommandLineGetFlag (Package, L"-i")) {\r
ExplainData = TRUE;\r
}\r
\r
- Temp = ShellCommandLineGetValue(Package, L"-s");\r
+ Temp = ShellCommandLineGetValue (Package, L"-s");\r
if (Temp != NULL) {\r
//\r
// Input converted to hexadecimal number.\r
//\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
- Segment = (UINT16) RetVal;\r
+ Segment = (UINT16)RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
// The first Argument(except "-i") is assumed to be Bus number, second\r
// to be Device number, and third to be Func number.\r
//\r
- Temp = ShellCommandLineGetRawValue(Package, 1);\r
+ Temp = ShellCommandLineGetRawValue (Package, 1);\r
if (Temp != NULL) {\r
//\r
// Input converted to hexadecimal number.\r
//\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
- Bus = (UINT16) RetVal;\r
+ Bus = (UINT16)RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
- if (Bus > MAX_BUS_NUMBER) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+ if (Bus > PCI_MAX_BUS) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
}\r
- Temp = ShellCommandLineGetRawValue(Package, 2);\r
+\r
+ Temp = ShellCommandLineGetRawValue (Package, 2);\r
if (Temp != NULL) {\r
//\r
// Input converted to hexadecimal number.\r
//\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
- Device = (UINT16) RetVal;\r
+ Device = (UINT16)RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
- if (Device > MAX_DEVICE_NUMBER){\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+ if (Device > PCI_MAX_DEVICE) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
}\r
\r
- Temp = ShellCommandLineGetRawValue(Package, 3);\r
+ Temp = ShellCommandLineGetRawValue (Package, 3);\r
if (Temp != NULL) {\r
//\r
// Input converted to hexadecimal number.\r
//\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
- Func = (UINT16) RetVal;\r
+ Func = (UINT16)RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
+ if (Func > PCI_MAX_FUNC) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
+ }\r
\r
- if (Func > MAX_FUNCTION_NUMBER){\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+ Temp = ShellCommandLineGetValue (Package, L"-ec");\r
+ if (Temp != NULL) {\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ ExtendedCapability = (UINT16)RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
// bus range covers the current bus\r
//\r
Status = PciFindProtocolInterface (\r
- HandleBuf,\r
- HandleCount,\r
- Segment,\r
- Bus,\r
- &IoDev\r
- );\r
+ HandleBuf,\r
+ HandleCount,\r
+ Segment,\r
+ Bus,\r
+ &IoDev\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(\r
- -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_NO_FIND),\r
+ gShellDebug1HiiHandle,\r
+ L"pci",\r
Segment,\r
Bus\r
- );\r
+ );\r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
\r
- Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
- Status = IoDev->Pci.Read (\r
- IoDev,\r
- EfiPciWidthUint8,\r
- Address,\r
- sizeof (ConfigSpace),\r
- &ConfigSpace\r
- );\r
+ Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
+ Status = IoDev->Pci.Read (\r
+ IoDev,\r
+ EfiPciWidthUint8,\r
+ Address,\r
+ sizeof (ConfigSpace),\r
+ &ConfigSpace\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_ACCESS_DENIED;\r
goto Done;\r
}\r
\r
mConfigSpace = &ConfigSpace;\r
- ShellPrintHiiEx(\r
+ ShellPrintHiiEx (\r
-1,\r
-1,\r
NULL,\r
Bus,\r
Device,\r
Func\r
- );\r
+ );\r
\r
//\r
// Dump standard header of configuration space\r
SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
\r
DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
- ShellPrintEx(-1,-1, L"\r\n");\r
+ ShellPrintEx (-1, -1, L"\r\n");\r
\r
//\r
// Dump device dependent Part of configuration space\r
SizeOfHeader,\r
sizeof (ConfigSpace) - SizeOfHeader,\r
ConfigSpace.Data\r
- );\r
+ );\r
+\r
+ ExtendedConfigSpace = NULL;\r
+ ExtendedConfigSize = 0;\r
+ PcieCapabilityPtr = LocatePciCapability (&ConfigSpace, EFI_PCI_CAPABILITY_ID_PCIEXP);\r
+ if (PcieCapabilityPtr != 0) {\r
+ ExtendedConfigSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
+ ExtendedConfigSpace = AllocatePool (ExtendedConfigSize);\r
+ if (ExtendedConfigSpace != NULL) {\r
+ Status = IoDev->Pci.Read (\r
+ IoDev,\r
+ EfiPciWidthUint32,\r
+ EFI_PCI_ADDRESS (Bus, Device, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET),\r
+ ExtendedConfigSize / sizeof (UINT32),\r
+ ExtendedConfigSpace\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ SHELL_FREE_NON_NULL (ExtendedConfigSpace);\r
+ }\r
+ }\r
+ }\r
+\r
+ if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r
+ //\r
+ // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r
+ //\r
+ ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
+\r
+ DumpHex (\r
+ 2,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET,\r
+ ExtendedConfigSize,\r
+ ExtendedConfigSpace\r
+ );\r
+ }\r
\r
//\r
// If "-i" appears in command line, interpret data in configuration space\r
//\r
if (ExplainData) {\r
- Status = PciExplainData (&ConfigSpace, Address, IoDev);\r
+ PciExplainPci (&ConfigSpace, Address, IoDev);\r
+ if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r
+ PciExplainPciExpress (\r
+ (PCI_CAPABILITY_PCIEXP *)((UINT8 *)&ConfigSpace + PcieCapabilityPtr),\r
+ ExtendedConfigSpace,\r
+ ExtendedConfigSize,\r
+ ExtendedCapability\r
+ );\r
+ }\r
}\r
}\r
+\r
Done:\r
if (HandleBuf != NULL) {\r
FreePool (HandleBuf);\r
}\r
+\r
if (Package != NULL) {\r
ShellCommandLineFreeVarList (Package);\r
}\r
+\r
mConfigSpace = NULL;\r
return ShellStatus;\r
}\r
**/\r
EFI_STATUS\r
PciFindProtocolInterface (\r
- IN EFI_HANDLE *HandleBuf,\r
- IN UINTN HandleCount,\r
- IN UINT16 Segment,\r
- IN UINT16 Bus,\r
- OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
+ IN EFI_HANDLE *HandleBuf,\r
+ IN UINTN HandleCount,\r
+ IN UINT16 Segment,\r
+ IN UINT16 Bus,\r
+ OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
)\r
{\r
- UINTN Index;\r
- EFI_STATUS Status;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
- UINT16 MinBus;\r
- UINT16 MaxBus;\r
- BOOLEAN IsEnd;\r
+ UINTN Index;\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
+ UINT16 MinBus;\r
+ UINT16 MaxBus;\r
+ BOOLEAN IsEnd;\r
\r
//\r
// Go through all handles, until the one meets the criteria is found\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// When Descriptors == NULL, the Configuration() is not implemented,\r
// so we only check the Segment number\r
//\r
- if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
+ if ((Descriptors == NULL) && (Segment == (*IoDev)->SegmentNumber)) {\r
return EFI_SUCCESS;\r
}\r
\r
break;\r
}\r
\r
- if (MinBus <= Bus && MaxBus >= Bus) {\r
+ if ((MinBus <= Bus) && (MaxBus >= Bus)) {\r
return EFI_SUCCESS;\r
}\r
}\r
**/\r
EFI_STATUS\r
PciGetProtocolAndResource (\r
- IN EFI_HANDLE Handle,\r
- OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
- OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
+ IN EFI_HANDLE Handle,\r
+ OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
+ OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
)\r
{\r
EFI_STATUS Status;\r
// Get inferface from protocol\r
//\r
Status = gBS->HandleProtocol (\r
- Handle,\r
- &gEfiPciRootBridgeIoProtocolGuid,\r
- (VOID**)IoDev\r
- );\r
+ Handle,\r
+ &gEfiPciRootBridgeIoProtocolGuid,\r
+ (VOID **)IoDev\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Call Configuration() to get address space descriptors\r
//\r
- Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
+ Status = (*IoDev)->Configuration (*IoDev, (VOID **)Descriptors);\r
if (Status == EFI_UNSUPPORTED) {\r
*Descriptors = NULL;\r
return EFI_SUCCESS;\r
-\r
} else {\r
return Status;\r
}\r
*MaxBus = PCI_MAX_BUS;\r
return EFI_SUCCESS;\r
}\r
+\r
//\r
// *Descriptors points to one or more address space descriptors, which\r
// ends with a end tagged descriptor. Examine each of the descriptors,\r
\r
while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
- *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
- *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
+ *MinBus = (UINT16)(*Descriptors)->AddrRangeMin;\r
+ *MaxBus = (UINT16)(*Descriptors)->AddrRangeMax;\r
(*Descriptors)++;\r
return (EFI_SUCCESS);\r
}\r
@param[in] ConfigSpace Data in PCI configuration space.\r
@param[in] Address Address used to access configuration space of this PCI device.\r
@param[in] IoDev Handle used to access configuration space of PCI device.\r
-\r
- @retval EFI_SUCCESS The command completed successfully.\r
**/\r
-EFI_STATUS\r
-PciExplainData (\r
- IN PCI_CONFIG_SPACE *ConfigSpace,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+VOID\r
+PciExplainPci (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
{\r
- PCI_COMMON_HEADER *Common;\r
- PCI_HEADER_TYPE HeaderType;\r
- EFI_STATUS Status;\r
- UINT8 CapPtr;\r
+ PCI_DEVICE_INDEPENDENT_REGION *Common;\r
+ PCI_HEADER_TYPE HeaderType;\r
\r
Common = &(ConfigSpace->Common);\r
\r
//\r
// Print Vendor Id and Device Id\r
//\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_LINE_VID_DID),\r
+ gShellDebug1HiiHandle,\r
INDEX_OF (&(Common->VendorId)),\r
Common->VendorId,\r
INDEX_OF (&(Common->DeviceId)),\r
Common->DeviceId\r
- );\r
+ );\r
\r
//\r
// Print register Command\r
//\r
// Print register Revision ID\r
//\r
- ShellPrintEx(-1, -1, L"\r\n");\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
- INDEX_OF (&(Common->RevisionId)),\r
- Common->RevisionId\r
- );\r
+ ShellPrintEx (-1, -1, L"\r\n");\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_LINE_RID),\r
+ gShellDebug1HiiHandle,\r
+ INDEX_OF (&(Common->RevisionID)),\r
+ Common->RevisionID\r
+ );\r
\r
//\r
// Print register BIST\r
//\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
- if ((Common->Bist & PCI_BIT_7) != 0) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));\r
+ if ((Common->BIST & BIT7) != 0) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
}\r
+\r
//\r
// Print register Cache Line Size\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Common->CacheLineSize)),\r
Common->CacheLineSize\r
- );\r
+ );\r
\r
//\r
// Print register Latency Timer\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
- Common->PrimaryLatencyTimer\r
- );\r
+ INDEX_OF (&(Common->LatencyTimer)),\r
+ Common->LatencyTimer\r
+ );\r
\r
//\r
// Print register Header Type\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Common->HeaderType)),\r
Common->HeaderType\r
- );\r
-\r
- if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
+ );\r
\r
+ if ((Common->HeaderType & BIT7) != 0) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
}\r
\r
- HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
+ HeaderType = (PCI_HEADER_TYPE)(UINT8)(Common->HeaderType & 0x7f);\r
switch (HeaderType) {\r
- case PciDevice:\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
- break;\r
+ case PciDevice:\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
+ break;\r
\r
- case PciP2pBridge:\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
- break;\r
+ case PciP2pBridge:\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
+ break;\r
\r
- case PciCardBusBridge:\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
- break;\r
+ case PciCardBusBridge:\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
+ break;\r
\r
- default:\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
- HeaderType = PciUndefined;\r
+ default:\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
+ HeaderType = PciUndefined;\r
}\r
\r
//\r
// Print register Class Code\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
- PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
+ PciPrintClassCode ((UINT8 *)Common->ClassCode, TRUE);\r
ShellPrintEx (-1, -1, L"\r\n");\r
-\r
- if (ShellGetExecutionBreakFlag()) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- //\r
- // Interpret remaining part of PCI configuration header depending on\r
- // HeaderType\r
- //\r
- CapPtr = 0;\r
- Status = EFI_SUCCESS;\r
- switch (HeaderType) {\r
- case PciDevice:\r
- Status = PciExplainDeviceData (\r
- &(ConfigSpace->NonCommon.Device),\r
- Address,\r
- IoDev\r
- );\r
- CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
- break;\r
-\r
- case PciP2pBridge:\r
- Status = PciExplainBridgeData (\r
- &(ConfigSpace->NonCommon.Bridge),\r
- Address,\r
- IoDev\r
- );\r
- CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
- break;\r
-\r
- case PciCardBusBridge:\r
- Status = PciExplainCardBusData (\r
- &(ConfigSpace->NonCommon.CardBus),\r
- Address,\r
- IoDev\r
- );\r
- CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
- break;\r
- case PciUndefined:\r
- default:\r
- break;\r
- }\r
- //\r
- // If Status bit4 is 1, dump or explain capability structure\r
- //\r
- if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
- PciExplainCapabilityStruct (IoDev, Address, CapPtr);\r
- }\r
-\r
- return Status;\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
- IN PCI_DEVICE_HEADER *Device,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
{\r
UINTN Index;\r
// exist. If these no Bar for this function, print "none", otherwise\r
// list detail information about this Bar.\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
\r
- BarExist = FALSE;\r
- BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
+ BarExist = FALSE;\r
+ BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
for (Index = 0; Index < BarCount; Index++) {\r
if (Device->Bar[Index] == 0) {\r
continue;\r
\r
if (!BarExist) {\r
BarExist = TRUE;\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
}\r
\r
Status = PciExplainBar (\r
- &(Device->Bar[Index]),\r
- &(mConfigSpace->Common.Command),\r
- Address,\r
- IoDev,\r
- &Index\r
- );\r
+ &(Device->Bar[Index]),\r
+ &(mConfigSpace->Common.Command),\r
+ Address,\r
+ IoDev,\r
+ &Index\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
break;\r
}\r
\r
if (!BarExist) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
-\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
} else {\r
ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
}\r
//\r
// Print register Expansion ROM Base Address\r
//\r
- if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
-\r
+ if ((Device->ExpansionRomBar & BIT0) == 0) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ExpansionRomBar)));\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->ROMBar)),\r
- Device->ROMBar\r
- );\r
+ INDEX_OF (&(Device->ExpansionRomBar)),\r
+ Device->ExpansionRomBar\r
+ );\r
}\r
+\r
//\r
// Print register Cardbus CIS ptr\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->CardBusCISPtr)),\r
- Device->CardBusCISPtr\r
- );\r
+ INDEX_OF (&(Device->CISPtr)),\r
+ Device->CISPtr\r
+ );\r
\r
//\r
// Print register Sub-vendor ID and subsystem ID\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->SubVendorId)),\r
- Device->SubVendorId\r
- );\r
+ INDEX_OF (&(Device->SubsystemVendorID)),\r
+ Device->SubsystemVendorID\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->SubSystemId)),\r
- Device->SubSystemId\r
- );\r
+ INDEX_OF (&(Device->SubsystemID)),\r
+ Device->SubsystemID\r
+ );\r
\r
//\r
// Print register Capabilities Ptr\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->CapabilitiesPtr)),\r
- Device->CapabilitiesPtr\r
- );\r
+ INDEX_OF (&(Device->CapabilityPtr)),\r
+ Device->CapabilityPtr\r
+ );\r
\r
//\r
// Print register Interrupt Line and interrupt pin\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Device->InterruptLine)),\r
Device->InterruptLine\r
- );\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Device->InterruptPin)),\r
Device->InterruptPin\r
- );\r
+ );\r
\r
//\r
// Print register Min_Gnt and Max_Lat\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_MIN_GNT),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Device->MinGnt)),\r
Device->MinGnt\r
- );\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_MAX_LAT),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Device->MaxLat)),\r
Device->MaxLat\r
- );\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
- IN PCI_BRIDGE_HEADER *Bridge,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
{\r
UINTN Index;\r
// exist. If these no Bar for this function, print "none", otherwise\r
// list detail information about this Bar.\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
\r
- BarExist = FALSE;\r
- BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
+ BarExist = FALSE;\r
+ BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
\r
for (Index = 0; Index < BarCount; Index++) {\r
if (Bridge->Bar[Index] == 0) {\r
\r
if (!BarExist) {\r
BarExist = TRUE;\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
}\r
\r
Status = PciExplainBar (\r
- &(Bridge->Bar[Index]),\r
- &(mConfigSpace->Common.Command),\r
- Address,\r
- IoDev,\r
- &Index\r
- );\r
+ &(Bridge->Bar[Index]),\r
+ &(mConfigSpace->Common.Command),\r
+ Address,\r
+ IoDev,\r
+ &Index\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
break;\r
}\r
\r
if (!BarExist) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
} else {\r
ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
}\r
//\r
// Expansion register ROM Base Address\r
//\r
- if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
-\r
+ if ((Bridge->ExpansionRomBAR & BIT0) == 0) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ExpansionRomBAR)));\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Bridge->ROMBar)),\r
- Bridge->ROMBar\r
- );\r
+ INDEX_OF (&(Bridge->ExpansionRomBAR)),\r
+ Bridge->ExpansionRomBAR\r
+ );\r
}\r
+\r
//\r
// Print Bus Numbers(Primary, Secondary, and Subordinate\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Bridge->PrimaryBus)),\r
INDEX_OF (&(Bridge->SecondaryBus)),\r
INDEX_OF (&(Bridge->SubordinateBus))\r
- );\r
+ );\r
\r
ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
\r
//\r
// Print register Secondary Latency Timer\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
Bridge->SecondaryLatencyTimer\r
- );\r
+ );\r
\r
//\r
// Print register Secondary Status\r
// types: I/O, memory, and pre-fetchable memory. For each resource type,\r
// base and limit address are listed.\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
//\r
// IO Base & Limit\r
//\r
- IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
+ IoAddress32 = (Bridge->IoBaseUpper16 << 16 | Bridge->IoBase << 8);\r
IoAddress32 &= 0xfffff000;\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_TWO_VARS),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Bridge->IoBase)),\r
IoAddress32\r
- );\r
+ );\r
\r
- IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
+ IoAddress32 = (Bridge->IoLimitUpper16 << 16 | Bridge->IoLimit << 8);\r
IoAddress32 |= 0x00000fff;\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
\r
//\r
// Memory Base & Limit\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_MEMORY),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Bridge->MemoryBase)),\r
(Bridge->MemoryBase << 16) & 0xfff00000\r
- );\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_ONE_VAR),\r
gShellDebug1HiiHandle,\r
(Bridge->MemoryLimit << 16) | 0x000fffff\r
- );\r
+ );\r
\r
//\r
// Pre-fetch-able Memory Base & Limit\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
- Bridge->PrefetchableBaseUpper,\r
- (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
- );\r
+ INDEX_OF (&(Bridge->PrefetchableMemoryBase)),\r
+ Bridge->PrefetchableBaseUpper32,\r
+ (Bridge->PrefetchableMemoryBase << 16) & 0xfff00000\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
gShellDebug1HiiHandle,\r
- Bridge->PrefetchableLimitUpper,\r
- (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
- );\r
+ Bridge->PrefetchableLimitUpper32,\r
+ (Bridge->PrefetchableMemoryLimit << 16) | 0x000fffff\r
+ );\r
\r
//\r
// Print register Capabilities Pointer\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
- Bridge->CapabilitiesPtr\r
- );\r
+ INDEX_OF (&(Bridge->CapabilityPtr)),\r
+ Bridge->CapabilityPtr\r
+ );\r
\r
//\r
// Print register Bridge Control\r
//\r
// Print register Interrupt Line & PIN\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Bridge->InterruptLine)),\r
Bridge->InterruptLine\r
- );\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(Bridge->InterruptPin)),\r
Bridge->InterruptPin\r
- );\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
PciExplainBar (\r
- IN UINT32 *Bar,\r
- IN UINT16 *Command,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN OUT UINTN *Index\r
+ IN UINT32 *Bar,\r
+ IN UINT16 *Command,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
+ IN OUT UINTN *Index\r
)\r
{\r
- UINT16 OldCommand;\r
- UINT16 NewCommand;\r
- UINT64 Bar64;\r
- UINT32 OldBar32;\r
- UINT32 NewBar32;\r
- UINT64 OldBar64;\r
- UINT64 NewBar64;\r
- BOOLEAN IsMem;\r
- BOOLEAN IsBar32;\r
- UINT64 RegAddress;\r
-\r
- IsBar32 = TRUE;\r
- Bar64 = 0;\r
- NewBar32 = 0;\r
- NewBar64 = 0;\r
+ UINT16 OldCommand;\r
+ UINT16 NewCommand;\r
+ UINT64 Bar64;\r
+ UINT32 OldBar32;\r
+ UINT32 NewBar32;\r
+ UINT64 OldBar64;\r
+ UINT64 NewBar64;\r
+ BOOLEAN IsMem;\r
+ BOOLEAN IsBar32;\r
+ UINT64 RegAddress;\r
+\r
+ IsBar32 = TRUE;\r
+ Bar64 = 0;\r
+ NewBar32 = 0;\r
+ NewBar64 = 0;\r
\r
//\r
// According the bar type, list detail about this bar, for example: 32 or\r
// 64 bits; pre-fetchable or not.\r
//\r
- if ((*Bar & PCI_BIT_0) == 0) {\r
+ if ((*Bar & BIT0) == 0) {\r
//\r
// This bar is of memory type\r
//\r
IsMem = TRUE;\r
\r
- if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
-\r
- } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
+ if (((*Bar & BIT1) == 0) && ((*Bar & BIT2) == 0)) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
+ } else if (((*Bar & BIT1) == 0) && ((*Bar & BIT2) != 0)) {\r
Bar64 = 0x0;\r
CopyMem (&Bar64, Bar, sizeof (UINT64));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32)RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32)(Bar64 & 0xfffffffffffffff0ULL));\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
IsBar32 = FALSE;\r
*Index += 1;\r
-\r
} else {\r
//\r
// Reserved\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
}\r
\r
- if ((*Bar & PCI_BIT_3) == 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
-\r
+ if ((*Bar & BIT3) == 0) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
}\r
-\r
} else {\r
//\r
// This bar is of io type\r
//\r
IsMem = FALSE;\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
ShellPrintEx (-1, -1, L"I/O ");\r
}\r
\r
//\r
// Disable io & mem access\r
//\r
- OldCommand = *Command;\r
- NewCommand = (UINT16) (OldCommand & 0xfffc);\r
- RegAddress = Address | INDEX_OF (Command);\r
+ OldCommand = *Command;\r
+ NewCommand = (UINT16)(OldCommand & 0xfffc);\r
+ RegAddress = Address | INDEX_OF (Command);\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
\r
RegAddress = Address | INDEX_OF (Bar);\r
// Read after write the BAR to get the size\r
//\r
if (IsBar32) {\r
- OldBar32 = *Bar;\r
- NewBar32 = 0xffffffff;\r
+ OldBar32 = *Bar;\r
+ NewBar32 = 0xffffffff;\r
\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
\r
if (IsMem) {\r
- NewBar32 = NewBar32 & 0xfffffff0;\r
- NewBar32 = (~NewBar32) + 1;\r
-\r
+ NewBar32 = NewBar32 & 0xfffffff0;\r
+ NewBar32 = (~NewBar32) + 1;\r
} else {\r
- NewBar32 = NewBar32 & 0xfffffffc;\r
- NewBar32 = (~NewBar32) + 1;\r
- NewBar32 = NewBar32 & 0x0000ffff;\r
+ NewBar32 = NewBar32 & 0xfffffffc;\r
+ NewBar32 = (~NewBar32) + 1;\r
+ NewBar32 = NewBar32 & 0x0000ffff;\r
}\r
} else {\r
-\r
OldBar64 = 0x0;\r
CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
NewBar64 = 0xffffffffffffffffULL;\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
\r
if (IsMem) {\r
- NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
- NewBar64 = (~NewBar64) + 1;\r
-\r
+ NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
+ NewBar64 = (~NewBar64) + 1;\r
} else {\r
- NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
- NewBar64 = (~NewBar64) + 1;\r
- NewBar64 = NewBar64 & 0x000000000000ffff;\r
+ NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
+ NewBar64 = (~NewBar64) + 1;\r
+ NewBar64 = NewBar64 & 0x000000000000ffff;\r
}\r
}\r
+\r
//\r
// Enable io & mem access\r
//\r
\r
if (IsMem) {\r
if (IsBar32) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
-\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32)RShiftU64 (NewBar64, 32));\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32)NewBar64);\r
ShellPrintEx (-1, -1, L" ");\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_RSHIFT),\r
gShellDebug1HiiHandle,\r
- (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
-\r
+ (UINT32)RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
+ );\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32)(NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
}\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
}\r
\r
return EFI_SUCCESS;\r
**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
- IN PCI_CARDBUS_HEADER *CardBus,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
{\r
BOOLEAN Io32Bit;\r
PCI_CARDBUS_DATA *CardBusData;\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->CardBusSocketReg)),\r
CardBus->CardBusSocketReg\r
- );\r
+ );\r
\r
//\r
// Print Secondary Status\r
// Print Bus Numbers(Primary bus number, CardBus bus number, and\r
// Subordinate bus number\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->PciBusNumber)),\r
INDEX_OF (&(CardBus->CardBusBusNumber)),\r
INDEX_OF (&(CardBus->SubordinateBusNumber))\r
- );\r
+ );\r
\r
ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
\r
//\r
// Print CardBus Latency Timer\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
CardBus->CardBusLatencyTimer\r
- );\r
+ );\r
\r
//\r
// Print Memory/Io ranges this cardbus bridge forwards\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_MEM_3),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->MemoryBase0)),\r
- CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
+ CardBus->BridgeControl & BIT8 ? L" Prefetchable" : L"Non-Prefetchable",\r
CardBus->MemoryBase0 & 0xfffff000,\r
CardBus->MemoryLimit0 | 0x00000fff\r
- );\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_MEM_3),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->MemoryBase1)),\r
- CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
+ CardBus->BridgeControl & BIT9 ? L" Prefetchable" : L"Non-Prefetchable",\r
CardBus->MemoryBase1 & 0xfffff000,\r
CardBus->MemoryLimit1 | 0x00000fff\r
- );\r
+ );\r
\r
- Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ Io32Bit = (BOOLEAN)(CardBus->IoBase0 & BIT0);\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_IO_2),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->IoBase0)),\r
Io32Bit ? L" 32 bit" : L" 16 bit",\r
CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
(CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
- );\r
+ );\r
\r
- Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ Io32Bit = (BOOLEAN)(CardBus->IoBase1 & BIT0);\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_IO_2),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->IoBase1)),\r
Io32Bit ? L" 32 bit" : L" 16 bit",\r
CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
(CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
- );\r
+ );\r
\r
//\r
// Print register Interrupt Line & PIN\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->InterruptLine)),\r
CardBus->InterruptLine,\r
INDEX_OF (&(CardBus->InterruptPin)),\r
CardBus->InterruptPin\r
- );\r
+ );\r
\r
//\r
// Print register Bridge Control\r
// bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
// Address.\r
//\r
- CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
+ CardBusData = (PCI_CARDBUS_DATA *)((UINT8 *)CardBus + sizeof (PCI_CARDBUS_CONTROL_REGISTER));\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBusData->SubVendorId)),\r
CardBusData->SubVendorId,\r
INDEX_OF (&(CardBusData->SubSystemId)),\r
CardBusData->SubSystemId\r
- );\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_OPTIONAL),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBusData->LegacyBase)),\r
CardBusData->LegacyBase\r
- );\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
PciExplainStatus (\r
- IN UINT16 *Status,\r
- IN BOOLEAN MainStatus,\r
- IN PCI_HEADER_TYPE HeaderType\r
+ IN UINT16 *Status,\r
+ IN BOOLEAN MainStatus,\r
+ IN PCI_HEADER_TYPE HeaderType\r
)\r
{\r
if (MainStatus) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
-\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
}\r
\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & BIT4) != 0);\r
\r
//\r
// Bit 5 is meaningless for CardBus Bridge\r
//\r
if (HeaderType == PciCardBusBridge) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
-\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r
}\r
\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & BIT7) != 0);\r
\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & BIT8) != 0);\r
//\r
// Bit 9 and bit 10 together decides the DEVSEL timing\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
- if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
-\r
- } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
-\r
- } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
-\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
+ if (((*Status & BIT9) == 0) && ((*Status & BIT10) == 0)) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
+ } else if (((*Status & BIT9) != 0) && ((*Status & BIT10) == 0)) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
+ } else if (((*Status & BIT9) == 0) && ((*Status & BIT10) != 0)) {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
}\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_11) != 0\r
- );\r
+ (*Status & BIT11) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_12) != 0\r
- );\r
+ (*Status & BIT12) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_13) != 0\r
- );\r
+ (*Status & BIT13) != 0\r
+ );\r
\r
if (MainStatus) {\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_14) != 0\r
- );\r
-\r
+ (*Status & BIT14) != 0\r
+ );\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_14) != 0\r
- );\r
+ (*Status & BIT14) != 0\r
+ );\r
}\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_15) != 0\r
- );\r
+ (*Status & BIT15) != 0\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
PciExplainCommand (\r
- IN UINT16 *Command\r
+ IN UINT16 *Command\r
)\r
{\r
//\r
// Print the binary value of register Command\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
\r
//\r
// Explain register Command bit by bit\r
//\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_0) != 0\r
- );\r
+ (*Command & BIT0) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_1) != 0\r
- );\r
+ (*Command & BIT1) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_2) != 0\r
- );\r
+ (*Command & BIT2) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_3) != 0\r
- );\r
+ (*Command & BIT3) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_4) != 0\r
- );\r
+ (*Command & BIT4) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_5) != 0\r
- );\r
+ (*Command & BIT5) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_6) != 0\r
- );\r
+ (*Command & BIT6) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_7) != 0\r
- );\r
+ (*Command & BIT7) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_8) != 0\r
- );\r
+ (*Command & BIT8) != 0\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_9) != 0\r
- );\r
+ (*Command & BIT9) != 0\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
PciExplainBridgeControl (\r
- IN UINT16 *BridgeControl,\r
- IN PCI_HEADER_TYPE HeaderType\r
+ IN UINT16 *BridgeControl,\r
+ IN PCI_HEADER_TYPE HeaderType\r
)\r
{\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
gShellDebug1HiiHandle,\r
INDEX_OF (BridgeControl),\r
*BridgeControl\r
- );\r
+ );\r
\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_0) != 0\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT0) != 0\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_1) != 0\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT1) != 0\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_2) != 0\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT2) != 0\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_3) != 0\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT3) != 0\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_5) != 0\r
- );\r
+ (*BridgeControl & BIT5) != 0\r
+ );\r
\r
//\r
// Register Bridge Control has some slight differences between P2P bridge\r
// and Cardbus bridge from bit 6 to bit 11.\r
//\r
if (HeaderType == PciP2pBridge) {\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_6) != 0\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT6) != 0\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_7) != 0\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT7) != 0\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT8) != 0 ? L"2^10" : L"2^15"\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT9) != 0 ? L"2^10" : L"2^15"\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_10) != 0\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT10) != 0\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_11) != 0\r
- );\r
-\r
+ (*BridgeControl & BIT11) != 0\r
+ );\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_6) != 0\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT6) != 0\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_7) != 0\r
- );\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+ (*BridgeControl & BIT7) != 0\r
+ );\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_10) != 0\r
- );\r
+ (*BridgeControl & BIT10) != 0\r
+ );\r
}\r
\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
- Print each capability structure.\r
+ Locate capability register block per capability ID.\r
\r
- @param[in] IoDev The pointer to the deivce.\r
- @param[in] Address The address to start at.\r
- @param[in] CapPtr The offset from the address.\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] CapabilityId The capability ID.\r
\r
- @retval EFI_SUCCESS The operation was successful.\r
+ @return The offset of the register block per capability ID,\r
+ or 0 if the register block cannot be found.\r
**/\r
-EFI_STATUS\r
-PciExplainCapabilityStruct (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapPtr\r
+UINT8\r
+LocatePciCapability (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT8 CapabilityId\r
)\r
{\r
- UINT8 CapabilityPtr;\r
- UINT16 CapabilityEntry;\r
- UINT8 CapabilityID;\r
- UINT64 RegAddress;\r
-\r
- CapabilityPtr = CapPtr;\r
+ UINT8 CapabilityPtr;\r
+ EFI_PCI_CAPABILITY_HDR *CapabilityEntry;\r
\r
//\r
- // Go through the Capability list\r
+ // To check the cpability of this device supports\r
//\r
- while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
- RegAddress = Address + CapabilityPtr;\r
- IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
+ if ((ConfigSpace->Common.Status & EFI_PCI_STATUS_CAPABILITY) == 0) {\r
+ return 0;\r
+ }\r
\r
- CapabilityID = (UINT8) CapabilityEntry;\r
+ switch ((PCI_HEADER_TYPE)(ConfigSpace->Common.HeaderType & 0x7f)) {\r
+ case PciDevice:\r
+ CapabilityPtr = ConfigSpace->NonCommon.Device.CapabilityPtr;\r
+ break;\r
+ case PciP2pBridge:\r
+ CapabilityPtr = ConfigSpace->NonCommon.Bridge.CapabilityPtr;\r
+ break;\r
+ case PciCardBusBridge:\r
+ CapabilityPtr = ConfigSpace->NonCommon.CardBus.Cap_Ptr;\r
+ break;\r
+ default:\r
+ return 0;\r
+ }\r
\r
- //\r
- // Explain PciExpress data\r
- //\r
- if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
- PciExplainPciExpress (IoDev, Address, CapabilityPtr);\r
- return EFI_SUCCESS;\r
+ while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
+ CapabilityEntry = (EFI_PCI_CAPABILITY_HDR *)((UINT8 *)ConfigSpace + CapabilityPtr);\r
+ if (CapabilityEntry->CapabilityID == CapabilityId) {\r
+ return CapabilityPtr;\r
}\r
+\r
//\r
- // Explain other capabilities here\r
+ // Certain PCI device may incorrectly have capability pointing to itself,\r
+ // break to avoid dead loop.\r
//\r
- CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
+ if (CapabilityPtr == CapabilityEntry->NextItemPtr) {\r
+ break;\r
+ }\r
+\r
+ CapabilityPtr = CapabilityEntry->NextItemPtr;\r
}\r
\r
- return EFI_SUCCESS;\r
+ return 0;\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieCapReg;\r
- CHAR16 *DevicePortType;\r
+ CHAR16 *DevicePortType;\r
\r
- PcieCapReg = PciExpressCap->PcieCapReg;\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Capability Version(3:0): %E0x%04x%N\r\n",\r
- PCIE_CAP_VERSION (PcieCapReg)\r
- );\r
- if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
- DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
+ PciExpressCap->Capability.Bits.Version\r
+ );\r
+ if (PciExpressCap->Capability.Bits.DevicePortType < ARRAY_SIZE (DevicePortTypeTable)) {\r
+ DevicePortType = DevicePortTypeTable[PciExpressCap->Capability.Bits.DevicePortType];\r
} else {\r
DevicePortType = L"Unknown Type";\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Device/PortType(7:4): %E%s%N\r\n",\r
DevicePortType\r
- );\r
+ );\r
//\r
// 'Slot Implemented' is only valid for:\r
// a) Root Port of PCI Express Root Complex, or\r
// b) Downstream Port of PCI Express Switch\r
//\r
- if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
- PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
- ShellPrintEx (-1, -1,\r
+ if ((PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_PORT) ||\r
+ (PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT))\r
+ {\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Slot Implemented(8): %E%d%N\r\n",\r
- PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
- );\r
+ PciExpressCap->Capability.Bits.SlotImplemented\r
+ );\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
- PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
- );\r
+ PciExpressCap->Capability.Bits.InterruptMessageNumber\r
+ );\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieCapReg;\r
- UINT32 PcieDeviceCap;\r
UINT8 DevicePortType;\r
UINT8 L0sLatency;\r
UINT8 L1Latency;\r
\r
- PcieCapReg = PciExpressCap->PcieCapReg;\r
- PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
- DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
+ DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
- if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
- ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
+ if (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize < 6) {\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize + 7));\r
} else {\r
ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
- PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceCapability.Bits.PhantomFunctions\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
- PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
- );\r
+ PciExpressCap->DeviceCapability.Bits.ExtendedTagField ? 8 : 5\r
+ );\r
//\r
// Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
//\r
if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
- L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
- L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
+ L0sLatency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL0sAcceptableLatency;\r
+ L1Latency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL1AcceptableLatency;\r
ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
if (L0sLatency < 4) {\r
ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
}\r
}\r
+\r
ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
if (L1Latency < 7) {\r
ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
}\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Role-based Error Reporting(15): %E%d%N\r\n",\r
- PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
- );\r
+ PciExpressCap->DeviceCapability.Bits.RoleBasedErrorReporting\r
+ );\r
//\r
// Only valid for Upstream Port:\r
// a) Captured Slot Power Limit Value\r
// b) Captured Slot Power Scale\r
//\r
- if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
- ShellPrintEx (-1, -1,\r
+ if (DevicePortType == PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) {\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
- PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitValue\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
- SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
- );\r
+ SlotPwrLmtScaleTable[PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitScale]\r
+ );\r
}\r
+\r
//\r
// Function Level Reset Capability is only valid for Endpoint\r
//\r
if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Function Level Reset Capability(28): %E%d%N\r\n",\r
- PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
- );\r
+ PciExpressCap->DeviceCapability.Bits.FunctionLevelReset\r
+ );\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieCapReg;\r
- UINT16 PcieDeviceControl;\r
-\r
- PcieCapReg = PciExpressCap->PcieCapReg;\r
- PcieDeviceControl = PciExpressCap->DeviceControl;\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
- PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceControl.Bits.CorrectableError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
- PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceControl.Bits.NonFatalError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
- PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceControl.Bits.FatalError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
- PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceControl.Bits.UnsupportedRequest\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
- PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
- );\r
+ PciExpressCap->DeviceControl.Bits.RelaxedOrdering\r
+ );\r
ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
- if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
- ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
+ if (PciExpressCap->DeviceControl.Bits.MaxPayloadSize < 6) {\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxPayloadSize + 7));\r
} else {\r
ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
- PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceControl.Bits.ExtendedTagField\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Phantom Functions Enable(9): %E%d%N\r\n",\r
- PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceControl.Bits.PhantomFunctions\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
- PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceControl.Bits.AuxPower\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Enable No Snoop(11): %E%d%N\r\n",\r
- PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
- );\r
+ PciExpressCap->DeviceControl.Bits.NoSnoop\r
+ );\r
ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
- if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
- ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
+ if (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize < 6) {\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize + 7));\r
} else {\r
ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
+\r
//\r
// Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
//\r
- if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
- ShellPrintEx (-1, -1,\r
+ if (PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE) {\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
- PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
- );\r
+ PciExpressCap->DeviceControl.Bits.BridgeConfigurationRetryOrFunctionLevelReset\r
+ );\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieDeviceStatus;\r
-\r
- PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Correctable Error Detected(0): %E%d%N\r\n",\r
- PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceStatus.Bits.CorrectableError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
- PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceStatus.Bits.NonFatalError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Fatal Error Detected(2): %E%d%N\r\n",\r
- PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceStatus.Bits.FatalError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Unsupported Request Detected(3): %E%d%N\r\n",\r
- PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceStatus.Bits.UnsupportedRequest\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" AUX Power Detected(4): %E%d%N\r\n",\r
- PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->DeviceStatus.Bits.AuxPower\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Transactions Pending(5): %E%d%N\r\n",\r
- PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
- );\r
+ PciExpressCap->DeviceStatus.Bits.TransactionsPending\r
+ );\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT32 PcieLinkCap;\r
- CHAR16 *MaxLinkSpeed;\r
- CHAR16 *AspmValue;\r
+ CHAR16 *MaxLinkSpeed;\r
+ CHAR16 *AspmValue;\r
\r
- PcieLinkCap = PciExpressCap->LinkCap;\r
- switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
+ switch (PciExpressCap->LinkCapability.Bits.MaxLinkSpeed) {\r
case 1:\r
MaxLinkSpeed = L"2.5 GT/s";\r
break;\r
case 3:\r
MaxLinkSpeed = L"8.0 GT/s";\r
break;\r
+ case 4:\r
+ MaxLinkSpeed = L"16.0 GT/s";\r
+ break;\r
+ case 5:\r
+ MaxLinkSpeed = L"32.0 GT/s";\r
+ break;\r
default:\r
- MaxLinkSpeed = L"Unknown";\r
+ MaxLinkSpeed = L"Reserved";\r
break;\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
MaxLinkSpeed\r
- );\r
- ShellPrintEx (-1, -1,\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
- PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
- );\r
- switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
+ PciExpressCap->LinkCapability.Bits.MaxLinkWidth\r
+ );\r
+ switch (PciExpressCap->LinkCapability.Bits.Aspm) {\r
case 0:\r
AspmValue = L"Not";\r
break;\r
AspmValue = L"Reserved";\r
break;\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
AspmValue\r
- );\r
- ShellPrintEx (-1, -1,\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
- L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
- );\r
- ShellPrintEx (-1, -1,\r
+ L0sLatencyStrTable[PciExpressCap->LinkCapability.Bits.L0sExitLatency]\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
- L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
- );\r
- ShellPrintEx (-1, -1,\r
+ L1LatencyStrTable[PciExpressCap->LinkCapability.Bits.L1ExitLatency]\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Clock Power Management(18): %E%d%N\r\n",\r
- PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkCapability.Bits.ClockPowerManagement\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
- PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkCapability.Bits.SurpriseDownError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
- PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkCapability.Bits.DataLinkLayerLinkActive\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
- PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkCapability.Bits.LinkBandwidthNotification\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Port Number(31:24): %E0x%02x%N\r\n",\r
- PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
- );\r
+ PciExpressCap->LinkCapability.Bits.PortNumber\r
+ );\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieLinkControl;\r
UINT8 DevicePortType;\r
\r
- PcieLinkControl = PciExpressCap->LinkControl;\r
- DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
- ShellPrintEx (-1, -1,\r
+ DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
- ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
- );\r
+ ASPMCtrlStrTable[PciExpressCap->LinkControl.Bits.AspmControl]\r
+ );\r
//\r
// RCB is not applicable to switches\r
//\r
- if (!IS_PCIE_SWITCH(DevicePortType)) {\r
- ShellPrintEx (-1, -1,\r
+ if (!IS_PCIE_SWITCH (DevicePortType)) {\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
- 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
- );\r
+ 1 << (PciExpressCap->LinkControl.Bits.ReadCompletionBoundary + 6)\r
+ );\r
}\r
+\r
//\r
// Link Disable is reserved on\r
// a) Endpoints\r
// c) Upstream Ports of Switches\r
//\r
if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
- DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
- DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
- ShellPrintEx (-1, -1,\r
+ (DevicePortType != PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) &&\r
+ (DevicePortType != PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE))\r
+ {\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Link Disable(4): %E%d%N\r\n",\r
- PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
- );\r
+ PciExpressCap->LinkControl.Bits.LinkDisable\r
+ );\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Common Clock Configuration(6): %E%d%N\r\n",\r
- PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkControl.Bits.CommonClockConfiguration\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Extended Synch(7): %E%d%N\r\n",\r
- PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkControl.Bits.ExtendedSynch\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Enable Clock Power Management(8): %E%d%N\r\n",\r
- PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkControl.Bits.ClockPowerManagement\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
- PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkControl.Bits.HardwareAutonomousWidthDisable\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
- PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkControl.Bits.LinkBandwidthManagementInterrupt\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
- PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
- );\r
+ PciExpressCap->LinkControl.Bits.LinkAutonomousBandwidthInterrupt\r
+ );\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieLinkStatus;\r
- CHAR16 *CurLinkSpeed;\r
+ CHAR16 *CurLinkSpeed;\r
\r
- PcieLinkStatus = PciExpressCap->LinkStatus;\r
- switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
+ switch (PciExpressCap->LinkStatus.Bits.CurrentLinkSpeed) {\r
case 1:\r
CurLinkSpeed = L"2.5 GT/s";\r
break;\r
case 3:\r
CurLinkSpeed = L"8.0 GT/s";\r
break;\r
+ case 4:\r
+ CurLinkSpeed = L"16.0 GT/s";\r
+ break;\r
+ case 5:\r
+ CurLinkSpeed = L"32.0 GT/s";\r
+ break;\r
default:\r
CurLinkSpeed = L"Reserved";\r
break;\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Current Link Speed(3:0): %E%s%N\r\n",\r
CurLinkSpeed\r
- );\r
- ShellPrintEx (-1, -1,\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
- PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkStatus.Bits.NegotiatedLinkWidth\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Link Training(11): %E%d%N\r\n",\r
- PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkStatus.Bits.LinkTraining\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Slot Clock Configuration(12): %E%d%N\r\n",\r
- PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkStatus.Bits.SlotClockConfiguration\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
- PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkStatus.Bits.DataLinkLayerLinkActive\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
- PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->LinkStatus.Bits.LinkBandwidthManagement\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
- PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
- );\r
+ PciExpressCap->LinkStatus.Bits.LinkAutonomousBandwidth\r
+ );\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT32 PcieSlotCap;\r
-\r
- PcieSlotCap = PciExpressCap->SlotCap;\r
-\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Attention Button Present(0): %E%d%N\r\n",\r
- PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.AttentionButton\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Power Controller Present(1): %E%d%N\r\n",\r
- PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.PowerController\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" MRL Sensor Present(2): %E%d%N\r\n",\r
- PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.MrlSensor\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Attention Indicator Present(3): %E%d%N\r\n",\r
- PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.AttentionIndicator\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Power Indicator Present(4): %E%d%N\r\n",\r
- PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.PowerIndicator\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
- PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.HotPlugSurprise\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Hot-Plug Capable(6): %E%d%N\r\n",\r
- PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.HotPlugCapable\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
- PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.SlotPowerLimitValue\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
- SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
- );\r
- ShellPrintEx (-1, -1,\r
+ SlotPwrLmtScaleTable[PciExpressCap->SlotCapability.Bits.SlotPowerLimitScale]\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
- PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.ElectromechanicalInterlock\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" No Command Completed Support(18): %E%d%N\r\n",\r
- PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotCapability.Bits.NoCommandCompleted\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Physical Slot Number(31:19): %E%d%N\r\n",\r
- PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
- );\r
+ PciExpressCap->SlotCapability.Bits.PhysicalSlotNumber\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieSlotControl;\r
-\r
- PcieSlotControl = PciExpressCap->SlotControl;\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
- PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotControl.Bits.AttentionButtonPressed\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
- PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotControl.Bits.PowerFaultDetected\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
- PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotControl.Bits.MrlSensorChanged\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
- PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotControl.Bits.PresenceDetectChanged\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
- PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotControl.Bits.CommandCompletedInterrupt\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
- PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotControl.Bits.HotPlugInterrupt\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
- IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
- );\r
- ShellPrintEx (-1, -1,\r
+ IndicatorTable[\r
+ PciExpressCap->SlotControl.Bits.AttentionIndicator]\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Power Indicator Control(9:8): %E%s%N\r\n",\r
- IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
- );\r
+ IndicatorTable[PciExpressCap->SlotControl.Bits.PowerIndicator]\r
+ );\r
ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
- if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
+ if (\r
+ PciExpressCap->SlotControl.Bits.PowerController)\r
+ {\r
ShellPrintEx (-1, -1, L"Off%N\r\n");\r
} else {\r
ShellPrintEx (-1, -1, L"On%N\r\n");\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
- PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotControl.Bits.ElectromechanicalInterlock\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
- PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
- );\r
+ PciExpressCap->SlotControl.Bits.DataLinkLayerStateChanged\r
+ );\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieSlotStatus;\r
-\r
- PcieSlotStatus = PciExpressCap->SlotStatus;\r
-\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Attention Button Pressed(0): %E%d%N\r\n",\r
- PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotStatus.Bits.AttentionButtonPressed\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Power Fault Detected(1): %E%d%N\r\n",\r
- PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotStatus.Bits.PowerFaultDetected\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" MRL Sensor Changed(2): %E%d%N\r\n",\r
- PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotStatus.Bits.MrlSensorChanged\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Presence Detect Changed(3): %E%d%N\r\n",\r
- PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->SlotStatus.Bits.PresenceDetectChanged\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Command Completed(4): %E%d%N\r\n",\r
- PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
- );\r
+ PciExpressCap->SlotStatus.Bits.CommandCompleted\r
+ );\r
ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
- if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
+ if (\r
+ PciExpressCap->SlotStatus.Bits.MrlSensor)\r
+ {\r
ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
} else {\r
ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
}\r
+\r
ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
- if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
+ if (\r
+ PciExpressCap->SlotStatus.Bits.PresenceDetect)\r
+ {\r
ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
} else {\r
ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
}\r
+\r
ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
- if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
+ if (\r
+ PciExpressCap->SlotStatus.Bits.ElectromechanicalInterlock)\r
+ {\r
ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
} else {\r
ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
}\r
- ShellPrintEx (-1, -1,\r
+\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
- PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
- );\r
+ PciExpressCap->SlotStatus.Bits.DataLinkLayerStateChanged\r
+ );\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieRootControl;\r
-\r
- PcieRootControl = PciExpressCap->RootControl;\r
-\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
- PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->RootControl.Bits.SystemErrorOnCorrectableError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
- PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->RootControl.Bits.SystemErrorOnNonFatalError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
- PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->RootControl.Bits.SystemErrorOnFatalError\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" PME Interrupt Enable(3): %E%d%N\r\n",\r
- PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->RootControl.Bits.PmeInterrupt\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
- PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
- );\r
+ PciExpressCap->RootControl.Bits.CrsSoftwareVisibility\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieRootCap;\r
-\r
- PcieRootCap = PciExpressCap->RsvdP;\r
-\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" CRS Software Visibility(0): %E%d%N\r\n",\r
- PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
- );\r
+ PciExpressCap->RootCapability.Bits.CrsSoftwareVisibility\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT32 PcieRootStatus;\r
-\r
- PcieRootStatus = PciExpressCap->RootStatus;\r
-\r
- ShellPrintEx (-1, -1,\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
- PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->RootStatus.Bits.PmeRequesterId\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" PME Status(16): %E%d%N\r\n",\r
- PCIE_CAP_PME_STATUS (PcieRootStatus)\r
- );\r
- ShellPrintEx (-1, -1,\r
+ PciExpressCap->RootStatus.Bits.PmeStatus\r
+ );\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
L" PME Pending(17): %E%d%N\r\n",\r
- PCIE_CAP_PME_PENDING (PcieRootStatus)\r
- );\r
+ PciExpressCap->RootStatus.Bits.PmePending\r
+ );\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
- Display Pcie device structure.\r
+ Function to interpret and print out the link control structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityLinkControl (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL),\r
+ gShellDebug1HiiHandle,\r
+ Header->RootComplexLinkCapabilities,\r
+ Header->RootComplexLinkControl,\r
+ Header->RootComplexLinkStatus\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the power budgeting structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityPowerBudgeting (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_POWER),\r
+ gShellDebug1HiiHandle,\r
+ Header->DataSelect,\r
+ Header->Data,\r
+ Header->PowerBudgetCapability\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the ACS structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityAcs (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r
+ UINT16 VectorSize;\r
+ UINT16 LoopCounter;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *)HeaderAddress;\r
+ VectorSize = 0;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ACS),\r
+ gShellDebug1HiiHandle,\r
+ Header->AcsCapability,\r
+ Header->AcsControl\r
+ );\r
+ if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL (Header)) {\r
+ VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE (Header);\r
+ if (VectorSize == 0) {\r
+ VectorSize = 256;\r
+ }\r
+\r
+ for (LoopCounter = 0; LoopCounter * 8 < VectorSize; LoopCounter++) {\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ACS2),\r
+ gShellDebug1HiiHandle,\r
+ LoopCounter + 1,\r
+ Header->EgressControlVectorArray[LoopCounter]\r
+ );\r
+ }\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the latency tolerance reporting structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LAT),\r
+ gShellDebug1HiiHandle,\r
+ Header->MaxSnoopLatency,\r
+ Header->MaxNoSnoopLatency\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the serial number structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilitySerialNumber (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_SN),\r
+ gShellDebug1HiiHandle,\r
+ Header->SerialNumber\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the RCRB structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityRcrb (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_RCRB),\r
+ gShellDebug1HiiHandle,\r
+ Header->VendorId,\r
+ Header->DeviceId,\r
+ Header->RcrbCapabilities,\r
+ Header->RcrbControl\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the vendor specific structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityVendorSpecific (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VEN),\r
+ gShellDebug1HiiHandle,\r
+ Header->VendorSpecificHeader\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE (Header),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the Event Collector Endpoint Association structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityECEA (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *)HeaderAddress;\r
\r
- @param[in] IoDev The pointer to the root pci protocol.\r
- @param[in] Address The Address to start at.\r
- @param[in] CapabilityPtr The offset from the address to start.\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ECEA),\r
+ gShellDebug1HiiHandle,\r
+ Header->AssociationBitmap\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the ARI structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityAri (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ARI),\r
+ gShellDebug1HiiHandle,\r
+ Header->AriCapability,\r
+ Header->AriControl\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the DPA structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r
+ UINT8 LinkCount;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_DPA),\r
+ gShellDebug1HiiHandle,\r
+ Header->DpaCapability,\r
+ Header->DpaLatencyIndicator,\r
+ Header->DpaStatus,\r
+ Header->DpaControl\r
+ );\r
+ for (LinkCount = 0; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX (Header) + 1; LinkCount++) {\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_DPA2),\r
+ gShellDebug1HiiHandle,\r
+ LinkCount+1,\r
+ Header->DpaPowerAllocationArray[LinkCount]\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX (Header),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the link declaration structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityLinkDeclaration (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r
+ UINT8 LinkCount;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR),\r
+ gShellDebug1HiiHandle,\r
+ Header->ElementSelfDescription\r
+ );\r
+\r
+ for (LinkCount = 0; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT (Header); LinkCount++) {\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2),\r
+ gShellDebug1HiiHandle,\r
+ LinkCount+1,\r
+ Header->LinkEntry[LinkCount]\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT (Header)-1)*sizeof (UINT32),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the Advanced Error Reporting structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityAer (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_AER),\r
+ gShellDebug1HiiHandle,\r
+ Header->UncorrectableErrorStatus,\r
+ Header->UncorrectableErrorMask,\r
+ Header->UncorrectableErrorSeverity,\r
+ Header->CorrectableErrorStatus,\r
+ Header->CorrectableErrorMask,\r
+ Header->AdvancedErrorCapabilitiesAndControl,\r
+ Header->HeaderLog[0],\r
+ Header->HeaderLog[1],\r
+ Header->HeaderLog[2],\r
+ Header->HeaderLog[3],\r
+ Header->RootErrorCommand,\r
+ Header->RootErrorStatus,\r
+ Header->ErrorSourceIdentification,\r
+ Header->CorrectableErrorSourceIdentification,\r
+ Header->TlpPrefixLog[0],\r
+ Header->TlpPrefixLog[1],\r
+ Header->TlpPrefixLog[2],\r
+ Header->TlpPrefixLog[3]\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the multicast structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityMulticast (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
+ IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST),\r
+ gShellDebug1HiiHandle,\r
+ Header->MultiCastCapability,\r
+ Header->MulticastControl,\r
+ Header->McBaseAddress,\r
+ Header->McReceiveAddress,\r
+ Header->McBlockAll,\r
+ Header->McBlockUntranslated,\r
+ Header->McOverlayBar\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the virtual channel and multi virtual channel structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityVirtualChannel (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r
+ UINT32 ItemCount;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE),\r
+ gShellDebug1HiiHandle,\r
+ Header->ExtendedVcCount,\r
+ Header->PortVcCapability1,\r
+ Header->PortVcCapability2,\r
+ Header->VcArbTableOffset,\r
+ Header->PortVcControl,\r
+ Header->PortVcStatus\r
+ );\r
+ for (ItemCount = 0; ItemCount < Header->ExtendedVcCount; ItemCount++) {\r
+ CapabilityItem = &Header->Capability[ItemCount];\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM),\r
+ gShellDebug1HiiHandle,\r
+ ItemCount+1,\r
+ CapabilityItem->VcResourceCapability,\r
+ CapabilityItem->PortArbTableOffset,\r
+ CapabilityItem->VcResourceControl,\r
+ CapabilityItem->VcResourceStatus\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY)\r
+ + Header->ExtendedVcCount * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the resizeable bar structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityResizeableBar (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r
+ UINT32 ItemCount;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *)HeaderAddress;\r
+\r
+ for (ItemCount = 0; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS (Header); ItemCount++) {\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR),\r
+ gShellDebug1HiiHandle,\r
+ ItemCount+1,\r
+ Header->Capability[ItemCount].ResizableBarCapability.Uint32,\r
+ Header->Capability[ItemCount].ResizableBarControl.Uint32\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ (UINT32)GET_NUMBER_RESIZABLE_BARS (Header) * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the TPH structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityTph (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_TPH),\r
+ gShellDebug1HiiHandle,\r
+ Header->TphRequesterCapability,\r
+ Header->TphRequesterControl\r
+ );\r
+ DumpHex (\r
+ 8,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)Header->TphStTable - (UINT8 *)HeadersBaseAddress),\r
+ GET_TPH_TABLE_SIZE (Header),\r
+ (VOID *)Header->TphStTable\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE (Header) - sizeof (UINT16),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the secondary PCIe capability structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilitySecondary (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
+ IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCap\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *)HeaderAddress;\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY),\r
+ gShellDebug1HiiHandle,\r
+ Header->LinkControl3.Uint32,\r
+ Header->LaneErrorStatus\r
+ );\r
+ DumpHex (\r
+ 8,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)Header->EqualizationControl - (UINT8 *)HeadersBaseAddress),\r
+ PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r
+ (VOID *)Header->EqualizationControl\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE) - sizeof (Header->EqualizationControl)\r
+ + PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r
+ (VOID *)(HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Display Pcie extended capability details\r
+\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] HeaderAddress The address of this capability header.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+PrintPciExtendedCapabilityDetails (\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r
+ )\r
+{\r
+ switch (HeaderAddress->CapabilityId) {\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
+ return PrintInterpretedExtendedCompatibilityAer (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
+ return PrintInterpretedExtendedCompatibilityLinkControl (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
+ return PrintInterpretedExtendedCompatibilityLinkDeclaration (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
+ return PrintInterpretedExtendedCompatibilitySerialNumber (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
+ return PrintInterpretedExtendedCompatibilityPowerBudgeting (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
+ return PrintInterpretedExtendedCompatibilityAcs (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
+ return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
+ return PrintInterpretedExtendedCompatibilityAri (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
+ return PrintInterpretedExtendedCompatibilityRcrb (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
+ return PrintInterpretedExtendedCompatibilityVendorSpecific (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
+ return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
+ return PrintInterpretedExtendedCompatibilityECEA (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
+ return PrintInterpretedExtendedCompatibilityVirtualChannel (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID:\r
+ //\r
+ // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
+ //\r
+ return PrintInterpretedExtendedCompatibilityMulticast (HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
+ return PrintInterpretedExtendedCompatibilityResizeableBar (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
+ return PrintInterpretedExtendedCompatibilityTph (HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
+ return PrintInterpretedExtendedCompatibilitySecondary (HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
+ default:\r
+ ShellPrintEx (\r
+ -1,\r
+ -1,\r
+ L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r
+ HeaderAddress->CapabilityId\r
+ );\r
+ return EFI_SUCCESS;\r
+ }\r
+}\r
+\r
+/**\r
+ Display Pcie device structure.\r
+\r
+ @param[in] PciExpressCap PCI Express capability buffer.\r
+ @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r
+ @param[in] ExtendedConfigSize PCI Express extended configuration size.\r
+ @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r
+**/\r
+VOID\r
PciExplainPciExpress (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapabilityPtr\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r
+ IN UINT8 *ExtendedConfigSpace,\r
+ IN UINTN ExtendedConfigSize,\r
+ IN CONST UINT16 ExtendedCapability\r
)\r
{\r
+ UINT8 DevicePortType;\r
+ UINTN Index;\r
+ UINT8 *RegAddr;\r
+ UINTN RegValue;\r
+ PCI_EXP_EXT_HDR *ExtHdr;\r
\r
- PCIE_CAP_STURCTURE PciExpressCap;\r
- EFI_STATUS Status;\r
- UINT64 CapRegAddress;\r
- UINT8 Bus;\r
- UINT8 Dev;\r
- UINT8 Func;\r
- UINT8 *ExRegBuffer;\r
- UINTN ExtendRegSize;\r
- UINT64 Pciex_Address;\r
- UINT8 DevicePortType;\r
- UINTN Index;\r
- UINT8 *RegAddr;\r
- UINTN RegValue;\r
-\r
- CapRegAddress = Address + CapabilityPtr;\r
- IoDev->Pci.Read (\r
- IoDev,\r
- EfiPciWidthUint32,\r
- CapRegAddress,\r
- sizeof (PciExpressCap) / sizeof (UINT32),\r
- &PciExpressCap\r
- );\r
-\r
- DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
+ DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
\r
ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
\r
for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
- if (ShellGetExecutionBreakFlag()) {\r
- goto Done;\r
+ if (ShellGetExecutionBreakFlag ()) {\r
+ return;\r
}\r
- RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
+\r
+ RegAddr = (UINT8 *)PciExpressCap + PcieExplainList[Index].Offset;\r
switch (PcieExplainList[Index].Width) {\r
case FieldWidthUINT8:\r
- RegValue = *(UINT8 *) RegAddr;\r
+ RegValue = *(UINT8 *)RegAddr;\r
break;\r
case FieldWidthUINT16:\r
- RegValue = *(UINT16 *) RegAddr;\r
+ RegValue = *(UINT16 *)RegAddr;\r
break;\r
case FieldWidthUINT32:\r
- RegValue = *(UINT32 *) RegAddr;\r
+ RegValue = *(UINT32 *)RegAddr;\r
break;\r
default:\r
RegValue = 0;\r
break;\r
}\r
- ShellPrintHiiEx(-1, -1, NULL,\r
+\r
+ ShellPrintHiiEx (\r
+ -1,\r
+ -1,\r
+ NULL,\r
PcieExplainList[Index].Token,\r
gShellDebug1HiiHandle,\r
PcieExplainList[Index].Offset,\r
RegValue\r
- );\r
+ );\r
if (PcieExplainList[Index].Func == NULL) {\r
continue;\r
}\r
+\r
switch (PcieExplainList[Index].Type) {\r
case PcieExplainTypeLink:\r
//\r
// a) Root Complex Integrated Endpoint\r
// b) Root Complex Event Collector\r
//\r
- if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
- DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
+ if ((DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) ||\r
+ (DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR))\r
+ {\r
continue;\r
}\r
+\r
break;\r
case PcieExplainTypeSlot:\r
//\r
// b) Downstream Port of PCI Express Switch\r
// and when SlotImplemented bit is set in PCIE cap register.\r
//\r
- if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
- DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
- !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
+ if (((DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT) &&\r
+ (DevicePortType != PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT)) ||\r
+ !PciExpressCap->Capability.Bits.SlotImplemented)\r
+ {\r
continue;\r
}\r
+\r
break;\r
case PcieExplainTypeRoot:\r
//\r
// Root registers are only valid for\r
// Root Port of PCI Express Root Complex\r
//\r
- if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
+ if (DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT) {\r
continue;\r
}\r
+\r
break;\r
default:\r
break;\r
}\r
- PcieExplainList[Index].Func (&PciExpressCap);\r
- }\r
-\r
- Bus = (UINT8) (RShiftU64 (Address, 24));\r
- Dev = (UINT8) (RShiftU64 (Address, 16));\r
- Func = (UINT8) (RShiftU64 (Address, 8));\r
-\r
- Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);\r
\r
- ExtendRegSize = 0x1000 - 0x100;\r
-\r
- ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
-\r
- //\r
- // PciRootBridgeIo protocol should support pci express extend space IO\r
- // (Begins at offset 0x100)\r
- //\r
- Status = IoDev->Pci.Read (\r
- IoDev,\r
- EfiPciWidthUint32,\r
- Pciex_Address,\r
- (ExtendRegSize) / sizeof (UINT32),\r
- (VOID *) (ExRegBuffer)\r
- );\r
- if (EFI_ERROR (Status)) {\r
- FreePool ((VOID *) ExRegBuffer);\r
- return EFI_UNSUPPORTED;\r
+ PcieExplainList[Index].Func (PciExpressCap);\r
}\r
- //\r
- // Start outputing PciEx extend space( 0xFF-0xFFF)\r
- //\r
- ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
\r
- if (ExRegBuffer != NULL) {\r
- DumpHex (\r
- 2,\r
- 0x100,\r
- ExtendRegSize,\r
- (VOID *) (ExRegBuffer)\r
- );\r
+ ExtHdr = (PCI_EXP_EXT_HDR *)ExtendedConfigSpace;\r
+ while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0 && ExtHdr->CapabilityId != 0xFFFF) {\r
+ //\r
+ // Process this item\r
+ //\r
+ if ((ExtendedCapability == 0xFFFF) || (ExtendedCapability == ExtHdr->CapabilityId)) {\r
+ //\r
+ // Print this item\r
+ //\r
+ PrintPciExtendedCapabilityDetails ((PCI_EXP_EXT_HDR *)ExtendedConfigSpace, ExtHdr, PciExpressCap);\r
+ }\r
\r
- FreePool ((VOID *) ExRegBuffer);\r
+ //\r
+ // Advance to the next item if it exists\r
+ //\r
+ if ((ExtHdr->NextCapabilityOffset != 0) &&\r
+ (ExtHdr->NextCapabilityOffset <= (UINT32)(ExtendedConfigSize + EFI_PCIE_CAPABILITY_BASE_OFFSET - sizeof (PCI_EXP_EXT_HDR))))\r
+ {\r
+ ExtHdr = (PCI_EXP_EXT_HDR *)(ExtendedConfigSpace + ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
+ } else {\r
+ break;\r
+ }\r
}\r
-\r
-Done:\r
- return EFI_SUCCESS;\r
}\r
projects / mirror_edk2.git / blobdiff