}\r
};\r
\r
-#define EFI_HEX_DISP_SIZE 32\r
-BOOLEAN\r
-PrivateDumpHex (\r
- IN UINTN Indent,\r
- IN UINTN Offset,\r
- IN UINTN DataSize,\r
- IN VOID *UserData\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Add page break feature to the DumpHex\r
-\r
-Arguments:\r
- Indent - The indent space\r
-\r
- Offset - The offset\r
-\r
- DataSize - The data size\r
-\r
- UserData - The data\r
-\r
-Returns:\r
-\r
- TRUE - The dump is broke\r
- FALSE - The dump is completed\r
-\r
-**/\r
-{\r
- UINTN DispSize;\r
- UINT8 *DispData;\r
-\r
- DispSize = EFI_HEX_DISP_SIZE;\r
- DispData = (UINT8 *) UserData;\r
-\r
- while (DataSize!=0) {\r
- if (ShellGetExecutionBreakFlag ()) {\r
- return TRUE;\r
- }\r
-\r
- if (DataSize > EFI_HEX_DISP_SIZE) {\r
- DataSize -= EFI_HEX_DISP_SIZE;\r
- } else {\r
- DispSize = DataSize;\r
- DataSize = 0;\r
- }\r
-\r
- DumpHex (Indent, Offset + DispData - (UINT8 *) UserData, DispSize, DispData);\r
- DispData += DispSize;\r
- }\r
-\r
- return FALSE;\r
-}\r
-\r
-//\r
-// Implemetations\r
-//\r
-VOID\r
-PciGetClassStrings (\r
- IN UINT32 ClassCode,\r
- IN OUT PCI_CLASS_STRINGS *ClassStrings\r
- )\r
-/*++\r
-Routine Description:\r
\r
+/**\r
Generates printable Unicode strings that represent PCI device class,\r
subclass and programmed I/F based on a value passed to the function.\r
\r
-Arguments:\r
-\r
- ClassCode Value representing the PCI "Class Code" register read from a\r
+ @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
PCI device. The encodings are:\r
bits 23:16 - Base Class Code\r
bits 15:8 - Sub-Class Code\r
bits 7:0 - Programming Interface\r
- ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
+ @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
printable class strings corresponding to ClassCode. The\r
caller must not modify the strings that are pointed by\r
the fields in ClassStrings.\r
-Returns:\r
-\r
- None\r
**/\r
+VOID\r
+PciGetClassStrings (\r
+ IN UINT32 ClassCode,\r
+ IN OUT PCI_CLASS_STRINGS *ClassStrings\r
+ )\r
{\r
INTN Index;\r
UINT8 Code;\r
return ;\r
}\r
\r
+/**\r
+ Print strings that represent PCI device class, subclass and programmed I/F.\r
+\r
+ @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
+ configuation space.\r
+ @param[in] IncludePIF If the printed string should include the programming I/F part\r
+**/\r
VOID\r
PciPrintClassCode (\r
IN UINT8 *ClassCodePtr,\r
IN BOOLEAN IncludePIF\r
)\r
-/*++\r
-Routine Description:\r
-\r
- Print strings that represent PCI device class, subclass and programmed I/F\r
-\r
-Arguments:\r
-\r
- ClassCodePtr Points to the memory which stores register Class Code in PCI\r
- configuation space.\r
- IncludePIF If the printed string should include the programming I/F part\r
-Returns:\r
-\r
- None\r
-**/\r
{\r
UINT32 ClassCode;\r
PCI_CLASS_STRINGS ClassStrings;\r
}\r
}\r
\r
-EFI_STATUS\r
-PciDump (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- );\r
+/**\r
+ This function finds out the protocol which is in charge of the given\r
+ segment, and its bus range covers the current bus number. It lookes\r
+ each instances of RootBridgeIoProtocol handle, until the one meets the\r
+ criteria is found.\r
+\r
+ @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
+ @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
+ @param[in] Segment Segment number of device we are dealing with.\r
+ @param[in] Bus Bus number of device we are dealing with.\r
+ @param[out] IoDev Handle used to access configuration space of PCI device.\r
\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter.\r
+\r
+**/\r
EFI_STATUS\r
PciFindProtocolInterface (\r
IN EFI_HANDLE *HandleBuf,\r
OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
);\r
\r
+/**\r
+ This function gets the protocol interface from the given handle, and\r
+ obtains its address space descriptors.\r
+\r
+ @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
+ @param[out] IoDev Handle used to access configuration space of PCI device.\r
+ @param[out] Descriptors Points to the address space descriptors.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully\r
+**/\r
EFI_STATUS\r
PciGetProtocolAndResource (\r
IN EFI_HANDLE Handle,\r
OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
);\r
\r
+/**\r
+ This function get the next bus range of given address space descriptors.\r
+ It also moves the pointer backward a node, to get prepared to be called\r
+ again.\r
+\r
+ @param[in, out] Descriptors Points to current position of a serial of address space\r
+ descriptors.\r
+ @param[out] MinBus The lower range of bus number.\r
+ @param[out] MaxBus The upper range of bus number.\r
+ @param[out] IsEnd Meet end of the serial of descriptors.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciGetNextBusRange (\r
IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
OUT BOOLEAN *IsEnd\r
);\r
\r
+/**\r
+ Explain the data in PCI configuration space. The part which is common for\r
+ PCI device and bridge is interpreted in this function. It calls other\r
+ functions to interpret data unique for device or bridge.\r
+\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainData (\r
IN PCI_CONFIG_SPACE *ConfigSpace,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
+/**\r
+ Explain the device specific part of data in PCI configuration space.\r
+\r
+ @param[in] Device Data in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
IN PCI_DEVICE_HEADER *Device,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
+/**\r
+ Explain the bridge specific part of data in PCI configuration space.\r
+\r
+ @param[in] Bridge Bridge specific data region in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
- IN PCI_BRIDGE_HEADER *Bridge,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ IN PCI_BRIDGE_HEADER *Bridge,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
+/**\r
+ Explain the Base Address Register(Bar) in PCI configuration space.\r
+\r
+ @param[in] Bar Points to the Base Address Register intended to interpret.\r
+ @param[in] Command Points to the register Command.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in, out] Index The Index.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBar (\r
IN UINT32 *Bar,\r
IN OUT UINTN *Index\r
);\r
\r
+/**\r
+ Explain the cardbus specific part of data in PCI configuration space.\r
+\r
+ @param[in] CardBus CardBus specific region of PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
IN PCI_CARDBUS_HEADER *CardBus,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
+/**\r
+ Explain each meaningful bit of register Status. The definition of Status is\r
+ slightly different depending on the PCI header type.\r
+\r
+ @param[in] Status Points to the content of register Status.\r
+ @param[in] MainStatus Indicates if this register is main status(not secondary\r
+ status).\r
+ @param[in] HeaderType Header type of this PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainStatus (\r
IN UINT16 *Status,\r
IN PCI_HEADER_TYPE HeaderType\r
);\r
\r
+/**\r
+ Explain each meaningful bit of register Command.\r
+\r
+ @param[in] Command Points to the content of register Command.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainCommand (\r
IN UINT16 *Command\r
);\r
\r
+/**\r
+ Explain each meaningful bit of register Bridge Control.\r
+\r
+ @param[in] BridgeControl Points to the content of register Bridge Control.\r
+ @param[in] HeaderType The headertype.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBridgeControl (\r
IN UINT16 *BridgeControl,\r
IN PCI_HEADER_TYPE HeaderType\r
);\r
\r
+/**\r
+ Print each capability structure.\r
+\r
+ @param[in] IoDev The pointer to the deivce.\r
+ @param[in] Address The address to start at.\r
+ @param[in] CapPtr The offset from the address.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
PciExplainCapabilityStruct (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
IN UINT8 CapPtr\r
);\r
\r
+/**\r
+ Display Pcie device structure.\r
+\r
+ @param[in] IoDev The pointer to the root pci protocol.\r
+ @param[in] Address The Address to start at.\r
+ @param[in] CapabilityPtr The offset from the address to start.\r
+**/\r
EFI_STATUS\r
PciExplainPciExpress (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
IN UINT8 CapabilityPtr\r
);\r
\r
+/**\r
+ Print out information of the capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device control information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
\r
+/**\r
+ Print out information of the device status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device link information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device link control information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
\r
+/**\r
+ Print out information of the device link status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device slot information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device slot control information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
\r
+/**\r
+ Print out information of the device slot status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
\r
+/**\r
+ Print out information of the device root information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device root capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device root status information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
\r
typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
\r
};\r
\r
\r
+/**\r
+ Function for 'pci' command.\r
+\r
+ @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
+ @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
+**/\r
SHELL_STATUS\r
EFIAPI\r
ShellCommandRunPci (\r
//\r
SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
\r
- PrivateDumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
+ DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
ShellPrintEx(-1,-1, L"\r\n");\r
\r
//\r
// Dump device dependent Part of configuration space\r
//\r
- PrivateDumpHex (\r
+ DumpHex (\r
2,\r
SizeOfHeader,\r
sizeof (ConfigSpace) - SizeOfHeader,\r
return ShellStatus;\r
}\r
\r
-EFI_STATUS\r
-PciFindProtocolInterface (\r
- IN EFI_HANDLE *HandleBuf,\r
- IN UINTN HandleCount,\r
- IN UINT16 Segment,\r
- IN UINT16 Bus,\r
- OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
This function finds out the protocol which is in charge of the given\r
segment, and its bus range covers the current bus number. It lookes\r
each instances of RootBridgeIoProtocol handle, until the one meets the\r
criteria is found.\r
\r
-Arguments:\r
+ @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
+ @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
+ @param[in] Segment Segment number of device we are dealing with.\r
+ @param[in] Bus Bus number of device we are dealing with.\r
+ @param[out] IoDev Handle used to access configuration space of PCI device.\r
\r
- HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles\r
- HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles\r
- Segment Segment number of device we are dealing with\r
- Bus Bus number of device we are dealing with\r
- IoDev Handle used to access configuration space of PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS - The command completed successfully\r
- EFI_INVALID_PARAMETER - Invalid parameter\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter.\r
\r
**/\r
+EFI_STATUS\r
+PciFindProtocolInterface (\r
+ IN EFI_HANDLE *HandleBuf,\r
+ IN UINTN HandleCount,\r
+ IN UINT16 Segment,\r
+ IN UINT16 Bus,\r
+ OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
+ )\r
{\r
UINTN Index;\r
EFI_STATUS Status;\r
}\r
}\r
\r
+/**\r
+ This function gets the protocol interface from the given handle, and\r
+ obtains its address space descriptors.\r
+\r
+ @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
+ @param[out] IoDev Handle used to access configuration space of PCI device.\r
+ @param[out] Descriptors Points to the address space descriptors.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully\r
+**/\r
EFI_STATUS\r
PciGetProtocolAndResource (\r
IN EFI_HANDLE Handle,\r
OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function gets the protocol interface from the given handle, and\r
- obtains its address space descriptors.\r
-\r
-Arguments:\r
-\r
- Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle\r
- IoDev Handle used to access configuration space of PCI device\r
- Descriptors Points to the address space descriptors\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
EFI_STATUS Status;\r
\r
}\r
}\r
\r
+/**\r
+ This function get the next bus range of given address space descriptors.\r
+ It also moves the pointer backward a node, to get prepared to be called\r
+ again.\r
+\r
+ @param[in, out] Descriptors Points to current position of a serial of address space\r
+ descriptors.\r
+ @param[out] MinBus The lower range of bus number.\r
+ @param[out] MaxBus The upper range of bus number.\r
+ @param[out] IsEnd Meet end of the serial of descriptors.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciGetNextBusRange (\r
IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
OUT UINT16 *MaxBus,\r
OUT BOOLEAN *IsEnd\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function get the next bus range of given address space descriptors.\r
- It also moves the pointer backward a node, to get prepared to be called\r
- again.\r
-\r
-Arguments:\r
-\r
- Descriptors points to current position of a serial of address space\r
- descriptors\r
- MinBus The lower range of bus number\r
- ManBus The upper range of bus number\r
- IsEnd Meet end of the serial of descriptors\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
*IsEnd = FALSE;\r
\r
return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-PciExplainData (\r
- IN PCI_CONFIG_SPACE *ConfigSpace,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
Explain the data in PCI configuration space. The part which is common for\r
PCI device and bridge is interpreted in this function. It calls other\r
functions to interpret data unique for device or bridge.\r
\r
-Arguments:\r
-\r
- ConfigSpace Data in PCI configuration space\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
\r
+ @retval EFI_SUCCESS The command completed successfully.\r
**/\r
+EFI_STATUS\r
+PciExplainData (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ )\r
{\r
PCI_COMMON_HEADER *Common;\r
PCI_HEADER_TYPE HeaderType;\r
//\r
// Print register BIST\r
//\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));\r
- if ((Common->BIST & PCI_BIT_7) != 0) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
+ if ((Common->Bist & PCI_BIT_7) != 0) {\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
} else {\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
}\r
);\r
CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
break;\r
+ case PciUndefined:\r
+ default:\r
+ break;\r
}\r
//\r
// If Status bit4 is 1, dump or explain capability structure\r
return Status;\r
}\r
\r
+/**\r
+ Explain the device specific part of data in PCI configuration space.\r
+\r
+ @param[in] Device Data in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
IN PCI_DEVICE_HEADER *Device,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain the device specific part of data in PCI configuration space.\r
-\r
-Arguments:\r
-\r
- Device Data in PCI configuration space\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
UINTN Index;\r
BOOLEAN BarExist;\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain the bridge specific part of data in PCI configuration space.\r
+\r
+ @param[in] Bridge Bridge specific data region in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
IN PCI_BRIDGE_HEADER *Bridge,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain the bridge specific part of data in PCI configuration space.\r
-\r
-Arguments:\r
-\r
- Bridge Bridge specific data region in PCI configuration space\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
UINTN Index;\r
BOOLEAN BarExist;\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain the Base Address Register(Bar) in PCI configuration space.\r
+\r
+ @param[in] Bar Points to the Base Address Register intended to interpret.\r
+ @param[in] Command Points to the register Command.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in, out] Index The Index.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBar (\r
IN UINT32 *Bar,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
IN OUT UINTN *Index\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain the Base Address Register(Bar) in PCI configuration space.\r
-\r
-Arguments:\r
-\r
- Bar Points to the Base Address Register intended to interpret\r
- Command Points to the register Command\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
- Index The Index\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
UINT16 OldCommand;\r
UINT16 NewCommand;\r
} else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
Bar64 = 0x0;\r
CopyMem (&Bar64, Bar, sizeof (UINT64));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0), 32));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
IsBar32 = FALSE;\r
\r
OldBar64 = 0x0;\r
CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
- NewBar64 = 0xffffffffffffffff;\r
+ NewBar64 = 0xffffffffffffffffULL;\r
\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
\r
if (IsMem) {\r
- NewBar64 = NewBar64 & 0xfffffffffffffff0;\r
+ NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
NewBar64 = (~NewBar64) + 1;\r
\r
} else {\r
- NewBar64 = NewBar64 & 0xfffffffffffffffc;\r
+ NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
NewBar64 = (~NewBar64) + 1;\r
NewBar64 = NewBar64 & 0x000000000000ffff;\r
}\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_RSHIFT),\r
gShellDebug1HiiHandle,\r
- RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1), 32)\r
+ RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
\r
}\r
} else {\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain the cardbus specific part of data in PCI configuration space.\r
+\r
+ @param[in] CardBus CardBus specific region of PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
IN PCI_CARDBUS_HEADER *CardBus,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain the cardbus specific part of data in PCI configuration space.\r
-\r
-Arguments:\r
-\r
- CardBus CardBus specific region of PCI configuration space\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
BOOLEAN Io32Bit;\r
PCI_CARDBUS_DATA *CardBusData;\r
INDEX_OF (&(CardBus->IoBase0)),\r
Io32Bit ? L" 32 bit" : L" 16 bit",\r
CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
- CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
+ (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
);\r
\r
Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
INDEX_OF (&(CardBus->IoBase1)),\r
Io32Bit ? L" 32 bit" : L" 16 bit",\r
CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
- CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
+ (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
);\r
\r
//\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain each meaningful bit of register Status. The definition of Status is\r
+ slightly different depending on the PCI header type.\r
+\r
+ @param[in] Status Points to the content of register Status.\r
+ @param[in] MainStatus Indicates if this register is main status(not secondary\r
+ status).\r
+ @param[in] HeaderType Header type of this PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainStatus (\r
IN UINT16 *Status,\r
IN BOOLEAN MainStatus,\r
IN PCI_HEADER_TYPE HeaderType\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain each meaningful bit of register Status. The definition of Status is\r
- slightly different depending on the PCI header type.\r
-\r
-Arguments:\r
-\r
- Status Points to the content of register Status\r
- MainStatus Indicates if this register is main status(not secondary\r
- status)\r
- HeaderType Header type of this PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
if (MainStatus) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-PciExplainCommand (\r
- IN UINT16 *Command\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
Explain each meaningful bit of register Command.\r
\r
-Arguments:\r
-\r
- Command Points to the content of register Command\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
+ @param[in] Command Points to the content of register Command.\r
\r
+ @retval EFI_SUCCESS The command completed successfully.\r
**/\r
+EFI_STATUS\r
+PciExplainCommand (\r
+ IN UINT16 *Command\r
+ )\r
{\r
//\r
// Print the binary value of register Command\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain each meaningful bit of register Bridge Control.\r
+\r
+ @param[in] BridgeControl Points to the content of register Bridge Control.\r
+ @param[in] HeaderType The headertype.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBridgeControl (\r
IN UINT16 *BridgeControl,\r
IN PCI_HEADER_TYPE HeaderType\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain each meaningful bit of register Bridge Control.\r
-\r
-Arguments:\r
-\r
- BridgeControl Points to the content of register Bridge Control\r
- HeaderType The headertype\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print each capability structure.\r
+\r
+ @param[in] IoDev The pointer to the deivce.\r
+ @param[in] Address The address to start at.\r
+ @param[in] CapPtr The offset from the address.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
PciExplainCapabilityStruct (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieCapReg;\r
CHAR16 *DevicePortType;\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieCapReg;\r
UINT32 PcieDeviceCap;\r
// Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
//\r
if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
- L0sLatency = (UINT8) PCIE_CAP_L0sLatency (PcieDeviceCap);\r
- L1Latency = (UINT8) PCIE_CAP_L1Latency (PcieDeviceCap);\r
+ L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
+ L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
Print (L" Endpoint L0s Acceptable Latency(8:6): ");\r
if (L0sLatency < 4) {\r
Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device control information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieCapReg;\r
UINT16 PcieDeviceControl;\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieDeviceStatus;\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device link information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT32 PcieLinkCap;\r
CHAR16 *SupLinkSpeeds;\r
- CHAR16 *ASPM;\r
+ CHAR16 *AspmValue;\r
\r
PcieLinkCap = PciExpressCap->LinkCap;\r
switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
);\r
switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
case 1:\r
- ASPM = L"L0s Entry";\r
+ AspmValue = L"L0s Entry";\r
break;\r
case 3:\r
- ASPM = L"L0s and L1";\r
+ AspmValue = L"L0s and L1";\r
break;\r
default:\r
- ASPM = L"Reserved";\r
+ AspmValue = L"Reserved";\r
break;\r
}\r
Print (\r
L" Active State Power Management Support(11:10): %E%s Supported%N\n",\r
- ASPM\r
+ AspmValue\r
);\r
Print (\r
L" L0s Exit Latency(14:12): %E%s%N\n",\r
- L0sLatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]\r
+ L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
);\r
Print (\r
L" L1 Exit Latency(17:15): %E%s%N\n",\r
- L1LatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]\r
+ L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
);\r
Print (\r
L" Clock Power Management(18): %E%d%N\n",\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device link control information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieLinkControl;\r
UINT8 DevicePortType;\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device link status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieLinkStatus;\r
CHAR16 *SupLinkSpeeds;\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device slot information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT32 PcieSlotCap;\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device slot control information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieSlotControl;\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device slot status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieSlotStatus;\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device root information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieRootControl;\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device root capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieRootCap;\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device root status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT32 PcieRootStatus;\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Display Pcie device structure.\r
+\r
+ @param[in] IoDev The pointer to the root pci protocol.\r
+ @param[in] Address The Address to start at.\r
+ @param[in] CapabilityPtr The offset from the address to start.\r
+**/\r
EFI_STATUS\r
PciExplainPciExpress (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
//\r
Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");\r
\r
- PrivateDumpHex (\r
- 2,\r
- 0x100,\r
- ExtendRegSize,\r
- (VOID *) (ExRegBuffer)\r
- );\r
+ if (ExRegBuffer != NULL) {\r
+ DumpHex (\r
+ 2,\r
+ 0x100,\r
+ ExtendRegSize,\r
+ (VOID *) (ExRegBuffer)\r
+ );\r
\r
- FreePool ((VOID *) ExRegBuffer);\r
+ FreePool ((VOID *) ExRegBuffer);\r
+ }\r
\r
Done:\r
return EFI_SUCCESS;\r
projects / mirror_edk2.git / blobdiff