ShellPkg: Fix pci command output of Max and Current Link Speed, and ASPM Support...

[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
index 3646209a81d76d3ba4c1947bf217fb70c3a631e0..e67c93f95bc1eba5927af8fadfa9e2d765fee1ac 100644 (file)
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
@@ -4051,32 +4051,41 @@ ExplainPcieLinkCap (
   )\r
 {\r
   UINT32 PcieLinkCap;\r
-  CHAR16 *SupLinkSpeeds;\r
+  CHAR16 *MaxLinkSpeed;\r
   CHAR16 *AspmValue;\r
 \r
   PcieLinkCap = PciExpressCap->LinkCap;\r
-  switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
+  switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
     case 1:\r
-      SupLinkSpeeds = L"2.5 GT/s";\r
+      MaxLinkSpeed = L"2.5 GT/s";\r
       break;\r
     case 2:\r
-      SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";\r
+      MaxLinkSpeed = L"5.0 GT/s";\r
+      break;\r
+    case 3:\r
+      MaxLinkSpeed = L"8.0 GT/s";\r
       break;\r
     default:\r
-      SupLinkSpeeds = L"Unknown";\r
+      MaxLinkSpeed = L"Unknown";\r
       break;\r
   }\r
   ShellPrintEx (-1, -1,\r
-    L"  Supported Link Speeds(3:0):                         %E%s supported%N\r\n",\r
-    SupLinkSpeeds\r
+    L"  Maximum Link Speed(3:0):                            %E%s%N\r\n",\r
+    MaxLinkSpeed\r
    );\r
   ShellPrintEx (-1, -1,\r
     L"  Maximum Link Width(9:4):                            %Ex%d%N\r\n",\r
     PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
    );\r
   switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
+    case 0:\r
+      AspmValue = L"Not";\r
+      break;\r
     case 1:\r
-      AspmValue = L"L0s Entry";\r
+      AspmValue = L"L0s";\r
+      break;\r
+    case 2:\r
+      AspmValue = L"L1";\r
       break;\r
     case 3:\r
       AspmValue = L"L0s and L1";\r
@@ -4204,23 +4213,26 @@ ExplainPcieLinkStatus (
   )\r
 {\r
   UINT16 PcieLinkStatus;\r
-  CHAR16 *SupLinkSpeeds;\r
+  CHAR16 *CurLinkSpeed;\r
 \r
   PcieLinkStatus = PciExpressCap->LinkStatus;\r
   switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
     case 1:\r
-      SupLinkSpeeds = L"2.5 GT/s";\r
+      CurLinkSpeed = L"2.5 GT/s";\r
       break;\r
     case 2:\r
-      SupLinkSpeeds = L"5.0 GT/s";\r
+      CurLinkSpeed = L"5.0 GT/s";\r
+      break;\r
+    case 3:\r
+      CurLinkSpeed = L"8.0 GT/s";\r
       break;\r
     default:\r
-      SupLinkSpeeds = L"Reserved";\r
+      CurLinkSpeed = L"Reserved";\r
       break;\r
   }\r
   ShellPrintEx (-1, -1,\r
     L"  Current Link Speed(3:0):                            %E%s%N\r\n",\r
-    SupLinkSpeeds\r
+    CurLinkSpeed\r
    );\r
   ShellPrintEx (-1, -1,\r
     L"  Negotiated Link Width(9:4):                         %Ex%d%N\r\n",\r