//\r
// The state machine of usb debug port\r
//\r
-#define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability\r
-#define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability\r
-#define USB3DBG_ENABLED 2 // The XHCI debug device is enabled\r
-#define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled\r
-#define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized\r
+#define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability\r
+#define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability\r
+#define USB3DBG_ENABLED 2 // The XHCI debug device is enabled\r
+#define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled\r
+#define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized\r
\r
-#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08\r
+#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08\r
\r
//\r
// MaxPacketSize for DbC Endpoint Descriptor IN and OUT\r
//\r
-#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400\r
+#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400\r
\r
#define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525\r
#define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A\r
#define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF\r
#define XHCI_DEBUG_DEVICE_REVISION 0x00\r
\r
-#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL\r
-#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000\r
+#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL\r
+#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000\r
\r
#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A\r
#define XHC_HCCPARAMS_OFFSET 0x10\r
#define XHC_CAPABILITY_ID_MASK 0xFF\r
#define XHC_NEXT_CAPABILITY_MASK 0xFF00\r
\r
-#define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1\r
-#define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset\r
-#define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset\r
-#define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset\r
+#define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1\r
+#define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset\r
+#define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset\r
+#define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset\r
\r
-#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
-#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
+#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
+#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
\r
-#define XHC_USBSTS_HALT BIT0\r
+#define XHC_USBSTS_HALT BIT0\r
\r
//\r
// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.\r
//\r
-#define DATA_TRANSFER_WRITE_TIMEOUT 0\r
-#define DATA_TRANSFER_READ_TIMEOUT 50000\r
-#define DATA_TRANSFER_POLL_TIMEOUT 1000\r
-#define XHC_DEBUG_PORT_1_MILLISECOND 1000\r
+#define DATA_TRANSFER_WRITE_TIMEOUT 0\r
+#define DATA_TRANSFER_READ_TIMEOUT 50000\r
+#define DATA_TRANSFER_POLL_TIMEOUT 1000\r
+#define XHC_DEBUG_PORT_1_MILLISECOND 1000\r
//\r
// XHCI port power off/on delay\r
//\r
-#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000\r
+#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000\r
\r
//\r
// USB debug device string descriptor (header size + unicode string length)\r
//\r
-#define STRING0_DESC_LEN 4\r
-#define MANU_DESC_LEN 12\r
-#define PRODUCT_DESC_LEN 40\r
-#define SERIAL_DESC_LEN 4\r
+#define STRING0_DESC_LEN 4\r
+#define MANU_DESC_LEN 12\r
+#define PRODUCT_DESC_LEN 40\r
+#define SERIAL_DESC_LEN 4\r
\r
//\r
// Debug Capability Register Offset\r
//\r
-#define XHC_DC_DCID 0x0\r
-#define XHC_DC_DCDB 0x4\r
-#define XHC_DC_DCERSTSZ 0x8\r
-#define XHC_DC_DCERSTBA 0x10\r
-#define XHC_DC_DCERDP 0x18\r
-#define XHC_DC_DCCTRL 0x20\r
-#define XHC_DC_DCST 0x24\r
-#define XHC_DC_DCPORTSC 0x28\r
-#define XHC_DC_DCCP 0x30\r
-#define XHC_DC_DCDDI1 0x38\r
-#define XHC_DC_DCDDI2 0x3C\r
+#define XHC_DC_DCID 0x0\r
+#define XHC_DC_DCDB 0x4\r
+#define XHC_DC_DCERSTSZ 0x8\r
+#define XHC_DC_DCERSTBA 0x10\r
+#define XHC_DC_DCERDP 0x18\r
+#define XHC_DC_DCCTRL 0x20\r
+#define XHC_DC_DCST 0x24\r
+#define XHC_DC_DCPORTSC 0x28\r
+#define XHC_DC_DCCP 0x30\r
+#define XHC_DC_DCDDI1 0x38\r
+#define XHC_DC_DCDDI2 0x3C\r
\r
-#define TRB_TYPE_LINK 6\r
+#define TRB_TYPE_LINK 6\r
\r
-#define ERST_NUMBER 0x01\r
-#define TR_RING_TRB_NUMBER 0x100\r
-#define EVENT_RING_TRB_NUMBER 0x200\r
+#define ERST_NUMBER 0x01\r
+#define TR_RING_TRB_NUMBER 0x100\r
+#define EVENT_RING_TRB_NUMBER 0x200\r
\r
-#define ED_BULK_OUT 2\r
-#define ED_BULK_IN 6\r
+#define ED_BULK_OUT 2\r
+#define ED_BULK_IN 6\r
\r
-#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))\r
-#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))\r
-#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
+#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))\r
+#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))\r
+#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
\r
//\r
// Endpoint Type (EP Type).\r
//\r
-#define ED_NOT_VALID 0\r
-#define ED_ISOCH_OUT 1\r
-#define ED_BULK_OUT 2\r
-#define ED_INTERRUPT_OUT 3\r
-#define ED_CONTROL_BIDIR 4\r
-#define ED_ISOCH_IN 5\r
-#define ED_BULK_IN 6\r
-#define ED_INTERRUPT_IN 7\r
+#define ED_NOT_VALID 0\r
+#define ED_ISOCH_OUT 1\r
+#define ED_BULK_OUT 2\r
+#define ED_INTERRUPT_OUT 3\r
+#define ED_CONTROL_BIDIR 4\r
+#define ED_ISOCH_IN 5\r
+#define ED_BULK_IN 6\r
+#define ED_INTERRUPT_IN 7\r
\r
//\r
// 6.4.5 TRB Completion Codes\r
//\r
// 6.4.6 TRB Types\r
//\r
-#define TRB_TYPE_NORMAL 1\r
-#define TRB_TYPE_SETUP_STAGE 2\r
-#define TRB_TYPE_DATA_STAGE 3\r
-#define TRB_TYPE_STATUS_STAGE 4\r
-#define TRB_TYPE_ISOCH 5\r
-#define TRB_TYPE_LINK 6\r
-#define TRB_TYPE_EVENT_DATA 7\r
-#define TRB_TYPE_NO_OP 8\r
-#define TRB_TYPE_EN_SLOT 9\r
-#define TRB_TYPE_DIS_SLOT 10\r
-#define TRB_TYPE_ADDRESS_DEV 11\r
-#define TRB_TYPE_CON_ENDPOINT 12\r
-#define TRB_TYPE_EVALU_CONTXT 13\r
-#define TRB_TYPE_RESET_ENDPOINT 14\r
-#define TRB_TYPE_STOP_ENDPOINT 15\r
-#define TRB_TYPE_SET_TR_DEQUE 16\r
-#define TRB_TYPE_RESET_DEV 17\r
-#define TRB_TYPE_GET_PORT_BANW 21\r
-#define TRB_TYPE_FORCE_HEADER 22\r
-#define TRB_TYPE_NO_OP_COMMAND 23\r
-#define TRB_TYPE_TRANS_EVENT 32\r
-#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
-#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
-#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
-#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
-#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
+#define TRB_TYPE_NORMAL 1\r
+#define TRB_TYPE_SETUP_STAGE 2\r
+#define TRB_TYPE_DATA_STAGE 3\r
+#define TRB_TYPE_STATUS_STAGE 4\r
+#define TRB_TYPE_ISOCH 5\r
+#define TRB_TYPE_LINK 6\r
+#define TRB_TYPE_EVENT_DATA 7\r
+#define TRB_TYPE_NO_OP 8\r
+#define TRB_TYPE_EN_SLOT 9\r
+#define TRB_TYPE_DIS_SLOT 10\r
+#define TRB_TYPE_ADDRESS_DEV 11\r
+#define TRB_TYPE_CON_ENDPOINT 12\r
+#define TRB_TYPE_EVALU_CONTXT 13\r
+#define TRB_TYPE_RESET_ENDPOINT 14\r
+#define TRB_TYPE_STOP_ENDPOINT 15\r
+#define TRB_TYPE_SET_TR_DEQUE 16\r
+#define TRB_TYPE_RESET_DEV 17\r
+#define TRB_TYPE_GET_PORT_BANW 21\r
+#define TRB_TYPE_FORCE_HEADER 22\r
+#define TRB_TYPE_NO_OP_COMMAND 23\r
+#define TRB_TYPE_TRANS_EVENT 32\r
+#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
+#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
+#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
+#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
+#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
\r
//\r
// Convert millisecond to microsecond.\r
//\r
-#define XHC_1_MILLISECOND (1000)\r
-#define XHC_POLL_DELAY (1000)\r
-#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
+#define XHC_1_MILLISECOND (1000)\r
+#define XHC_POLL_DELAY (1000)\r
+#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
\r
-#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
-#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
-#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.\r
-#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
+#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
+#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
+#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.\r
+#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
\r
//\r
// Transfer types, used in URB to identify the transfer type\r
//\r
-#define XHC_CTRL_TRANSFER 0x01\r
-#define XHC_BULK_TRANSFER 0x02\r
-#define XHC_INT_TRANSFER_SYNC 0x04\r
-#define XHC_INT_TRANSFER_ASYNC 0x08\r
-#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
+#define XHC_CTRL_TRANSFER 0x01\r
+#define XHC_BULK_TRANSFER 0x02\r
+#define XHC_INT_TRANSFER_SYNC 0x04\r
+#define XHC_INT_TRANSFER_ASYNC 0x08\r
+#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
\r
//\r
// USB Transfer Results\r
//\r
-#define EFI_USB_NOERROR 0x00\r
-#define EFI_USB_ERR_NOTEXECUTE 0x01\r
-#define EFI_USB_ERR_STALL 0x02\r
-#define EFI_USB_ERR_BUFFER 0x04\r
-#define EFI_USB_ERR_BABBLE 0x08\r
-#define EFI_USB_ERR_NAK 0x10\r
-#define EFI_USB_ERR_CRC 0x20\r
-#define EFI_USB_ERR_TIMEOUT 0x40\r
-#define EFI_USB_ERR_BITSTUFF 0x80\r
-#define EFI_USB_ERR_SYSTEM 0x100\r
+#define EFI_USB_NOERROR 0x00\r
+#define EFI_USB_ERR_NOTEXECUTE 0x01\r
+#define EFI_USB_ERR_STALL 0x02\r
+#define EFI_USB_ERR_BUFFER 0x04\r
+#define EFI_USB_ERR_BABBLE 0x08\r
+#define EFI_USB_ERR_NAK 0x10\r
+#define EFI_USB_ERR_CRC 0x20\r
+#define EFI_USB_ERR_TIMEOUT 0x40\r
+#define EFI_USB_ERR_BITSTUFF 0x80\r
+#define EFI_USB_ERR_SYSTEM 0x100\r
\r
#pragma pack(1)\r
\r
// 7.6.9.2 When used by the DbC it is always a 64 byte data structure\r
//\r
typedef struct _ENDPOINT_CONTEXT_64 {\r
- UINT32 EPState:3;\r
- UINT32 RsvdZ1:5;\r
- UINT32 Mult:2; // set to 0\r
- UINT32 MaxPStreams:5; // set to 0\r
- UINT32 LSA:1; // set to 0\r
- UINT32 Interval:8; // set to 0\r
- UINT32 RsvdZ2:8;\r
-\r
- UINT32 RsvdZ3:1;\r
- UINT32 CErr:2;\r
- UINT32 EPType:3;\r
- UINT32 RsvdZ4:1;\r
- UINT32 HID:1; // set to 0\r
- UINT32 MaxBurstSize:8;\r
- UINT32 MaxPacketSize:16;\r
-\r
- UINT32 PtrLo;\r
-\r
- UINT32 PtrHi;\r
-\r
- UINT32 AverageTRBLength:16;\r
- UINT32 MaxESITPayload:16; // set to 0\r
-\r
- UINT32 RsvdZ5; // Reserved\r
- UINT32 RsvdZ6;\r
- UINT32 RsvdZ7;\r
-\r
- UINT32 RsvdZ8;\r
- UINT32 RsvdZ9;\r
- UINT32 RsvdZ10;\r
- UINT32 RsvdZ11;\r
-\r
- UINT32 RsvdZ12;\r
- UINT32 RsvdZ13;\r
- UINT32 RsvdZ14;\r
- UINT32 RsvdZ15;\r
+ UINT32 EPState : 3;\r
+ UINT32 RsvdZ1 : 5;\r
+ UINT32 Mult : 2; // set to 0\r
+ UINT32 MaxPStreams : 5; // set to 0\r
+ UINT32 LSA : 1; // set to 0\r
+ UINT32 Interval : 8; // set to 0\r
+ UINT32 RsvdZ2 : 8;\r
+\r
+ UINT32 RsvdZ3 : 1;\r
+ UINT32 CErr : 2;\r
+ UINT32 EPType : 3;\r
+ UINT32 RsvdZ4 : 1;\r
+ UINT32 HID : 1; // set to 0\r
+ UINT32 MaxBurstSize : 8;\r
+ UINT32 MaxPacketSize : 16;\r
+\r
+ UINT32 PtrLo;\r
+\r
+ UINT32 PtrHi;\r
+\r
+ UINT32 AverageTRBLength : 16;\r
+ UINT32 MaxESITPayload : 16; // set to 0\r
+\r
+ UINT32 RsvdZ5; // Reserved\r
+ UINT32 RsvdZ6;\r
+ UINT32 RsvdZ7;\r
+\r
+ UINT32 RsvdZ8;\r
+ UINT32 RsvdZ9;\r
+ UINT32 RsvdZ10;\r
+ UINT32 RsvdZ11;\r
+\r
+ UINT32 RsvdZ12;\r
+ UINT32 RsvdZ13;\r
+ UINT32 RsvdZ14;\r
+ UINT32 RsvdZ15;\r
} ENDPOINT_CONTEXT_64;\r
\r
//\r
// Rings, and to define the Data stage information for Control Transfer Rings.\r
//\r
typedef struct _TRANSFER_TRB_NORMAL {\r
- UINT32 TRBPtrLo;\r
-\r
- UINT32 TRBPtrHi;\r
-\r
- UINT32 Length:17;\r
- UINT32 TDSize:5;\r
- UINT32 IntTarget:10;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 ENT:1;\r
- UINT32 ISP:1;\r
- UINT32 NS:1;\r
- UINT32 CH:1;\r
- UINT32 IOC:1;\r
- UINT32 IDT:1;\r
- UINT32 RsvdZ1:2;\r
- UINT32 BEI:1;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ2:16;\r
+ UINT32 TRBPtrLo;\r
+\r
+ UINT32 TRBPtrHi;\r
+\r
+ UINT32 Length : 17;\r
+ UINT32 TDSize : 5;\r
+ UINT32 IntTarget : 10;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 ENT : 1;\r
+ UINT32 ISP : 1;\r
+ UINT32 NS : 1;\r
+ UINT32 CH : 1;\r
+ UINT32 IOC : 1;\r
+ UINT32 IDT : 1;\r
+ UINT32 RsvdZ1 : 2;\r
+ UINT32 BEI : 1;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ2 : 16;\r
} TRANSFER_TRB_NORMAL;\r
\r
//\r
// for more information on the use and operation of Transfer Events.\r
//\r
typedef struct _EVT_TRB_TRANSFER {\r
- UINT32 TRBPtrLo;\r
+ UINT32 TRBPtrLo;\r
\r
- UINT32 TRBPtrHi;\r
+ UINT32 TRBPtrHi;\r
\r
- UINT32 Length:24;\r
- UINT32 Completecode:8;\r
+ UINT32 Length : 24;\r
+ UINT32 Completecode : 8;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ1:1;\r
- UINT32 ED:1;\r
- UINT32 RsvdZ2:7;\r
- UINT32 Type:6;\r
- UINT32 EndpointId:5;\r
- UINT32 RsvdZ3:3;\r
- UINT32 SlotId:8;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ1 : 1;\r
+ UINT32 ED : 1;\r
+ UINT32 RsvdZ2 : 7;\r
+ UINT32 Type : 6;\r
+ UINT32 EndpointId : 5;\r
+ UINT32 RsvdZ3 : 3;\r
+ UINT32 SlotId : 8;\r
} EVT_TRB_TRANSFER;\r
\r
//\r
// A Link TRB provides support for non-contiguous TRB Rings.\r
//\r
typedef struct _LINK_TRB {\r
- UINT32 PtrLo;\r
+ UINT32 PtrLo;\r
\r
- UINT32 PtrHi;\r
+ UINT32 PtrHi;\r
\r
- UINT32 RsvdZ1:22;\r
- UINT32 InterTarget:10;\r
+ UINT32 RsvdZ1 : 22;\r
+ UINT32 InterTarget : 10;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 TC:1;\r
- UINT32 RsvdZ2:2;\r
- UINT32 CH:1;\r
- UINT32 IOC:1;\r
- UINT32 RsvdZ3:4;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ4:16;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 TC : 1;\r
+ UINT32 RsvdZ2 : 2;\r
+ UINT32 CH : 1;\r
+ UINT32 IOC : 1;\r
+ UINT32 RsvdZ3 : 4;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ4 : 16;\r
} LINK_TRB;\r
\r
//\r
// TRB Template: 16 bytes\r
//\r
typedef struct _TRB_TEMPLATE {\r
- UINT32 Parameter1;\r
+ UINT32 Parameter1;\r
\r
- UINT32 Parameter2;\r
+ UINT32 Parameter2;\r
\r
- UINT32 Status;\r
+ UINT32 Status;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ1:9;\r
- UINT32 Type:6;\r
- UINT32 Control:16;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ1 : 9;\r
+ UINT32 Type : 6;\r
+ UINT32 Control : 16;\r
} TRB_TEMPLATE;\r
\r
//\r
// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes\r
//\r
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
- UINT32 PtrLo;\r
- UINT32 PtrHi;\r
- UINT32 RingTrbSize:16;\r
- UINT32 RsvdZ1:16;\r
- UINT32 RsvdZ2;\r
+ UINT32 PtrLo;\r
+ UINT32 PtrHi;\r
+ UINT32 RingTrbSize : 16;\r
+ UINT32 RsvdZ1 : 16;\r
+ UINT32 RsvdZ2;\r
} EVENT_RING_SEG_TABLE_ENTRY;\r
\r
//\r
// Size: 40 bytes\r
//\r
typedef struct _EVENT_RING {\r
- EFI_PHYSICAL_ADDRESS ERSTBase;\r
- EFI_PHYSICAL_ADDRESS EventRingSeg0;\r
- UINT32 TrbNumber;\r
- EFI_PHYSICAL_ADDRESS EventRingEnqueue;\r
- EFI_PHYSICAL_ADDRESS EventRingDequeue;\r
- UINT32 EventRingCCS;\r
+ EFI_PHYSICAL_ADDRESS ERSTBase;\r
+ EFI_PHYSICAL_ADDRESS EventRingSeg0;\r
+ UINT32 TrbNumber;\r
+ EFI_PHYSICAL_ADDRESS EventRingEnqueue;\r
+ EFI_PHYSICAL_ADDRESS EventRingDequeue;\r
+ UINT32 EventRingCCS;\r
} EVENT_RING;\r
\r
// Size: 32 bytes\r
typedef struct _TRANSFER_RING {\r
- EFI_PHYSICAL_ADDRESS RingSeg0;\r
- UINT32 TrbNumber;\r
- EFI_PHYSICAL_ADDRESS RingEnqueue;\r
- EFI_PHYSICAL_ADDRESS RingDequeue;\r
- UINT32 RingPCS;\r
+ EFI_PHYSICAL_ADDRESS RingSeg0;\r
+ UINT32 TrbNumber;\r
+ EFI_PHYSICAL_ADDRESS RingEnqueue;\r
+ EFI_PHYSICAL_ADDRESS RingDequeue;\r
+ UINT32 RingPCS;\r
} TRANSFER_RING;\r
\r
//\r
// Size: 64 bytes\r
//\r
typedef struct _DBC_INFO_CONTEXT {\r
- UINT64 String0DescAddress;\r
- UINT64 ManufacturerStrDescAddress;\r
- UINT64 ProductStrDescAddress;\r
- UINT64 SerialNumberStrDescAddress;\r
- UINT64 String0Length:8;\r
- UINT64 ManufacturerStrLength:8;\r
- UINT64 ProductStrLength:8;\r
- UINT64 SerialNumberStrLength:8;\r
- UINT64 RsvdZ1:32;\r
- UINT64 RsvdZ2;\r
- UINT64 RsvdZ3;\r
- UINT64 RsvdZ4;\r
+ UINT64 String0DescAddress;\r
+ UINT64 ManufacturerStrDescAddress;\r
+ UINT64 ProductStrDescAddress;\r
+ UINT64 SerialNumberStrDescAddress;\r
+ UINT64 String0Length : 8;\r
+ UINT64 ManufacturerStrLength : 8;\r
+ UINT64 ProductStrLength : 8;\r
+ UINT64 SerialNumberStrLength : 8;\r
+ UINT64 RsvdZ1 : 32;\r
+ UINT64 RsvdZ2;\r
+ UINT64 RsvdZ3;\r
+ UINT64 RsvdZ4;\r
} DBC_INFO_CONTEXT;\r
\r
//\r
// Debug Capability Context Data Structure: 192 bytes\r
//\r
typedef struct _XHC_DC_CONTEXT {\r
- DBC_INFO_CONTEXT DbcInfoContext;\r
- ENDPOINT_CONTEXT_64 EpOutContext;\r
- ENDPOINT_CONTEXT_64 EpInContext;\r
+ DBC_INFO_CONTEXT DbcInfoContext;\r
+ ENDPOINT_CONTEXT_64 EpOutContext;\r
+ ENDPOINT_CONTEXT_64 EpInContext;\r
} XHC_DC_CONTEXT;\r
\r
//\r
// Size: 16 bytes\r
//\r
typedef union _TRB {\r
- TRB_TEMPLATE TrbTemplate;\r
- TRANSFER_TRB_NORMAL TrbNormal;\r
+ TRB_TEMPLATE TrbTemplate;\r
+ TRANSFER_TRB_NORMAL TrbNormal;\r
} TRB;\r
\r
///\r
//\r
// Transfer data buffer\r
//\r
- EFI_PHYSICAL_ADDRESS Data;\r
- UINT32 DataLen;\r
+ EFI_PHYSICAL_ADDRESS Data;\r
+ UINT32 DataLen;\r
\r
//\r
// Execute result\r
//\r
- UINT32 Result;\r
+ UINT32 Result;\r
//\r
// Completed data length\r
//\r
- UINT32 Completed;\r
+ UINT32 Completed;\r
//\r
// Tranfer Ring info\r
//\r
- EFI_PHYSICAL_ADDRESS Ring;\r
- EFI_PHYSICAL_ADDRESS Trb;\r
- BOOLEAN Finished;\r
- EFI_USB_DATA_DIRECTION Direction;\r
+ EFI_PHYSICAL_ADDRESS Ring;\r
+ EFI_PHYSICAL_ADDRESS Trb;\r
+ BOOLEAN Finished;\r
+ EFI_USB_DATA_DIRECTION Direction;\r
} URB;\r
\r
typedef struct _USB3_DEBUG_PORT_INSTANCE {\r
- UINT8 Initialized;\r
+ UINT8 Initialized;\r
\r
//\r
// The flag indicates debug capability is supported\r
//\r
- BOOLEAN DebugSupport;\r
+ BOOLEAN DebugSupport;\r
\r
//\r
// The flag indicates debug device is ready\r
//\r
- BOOLEAN Ready;\r
+ BOOLEAN Ready;\r
\r
//\r
// The flag indicates the instance is from HOB\r
//\r
- BOOLEAN FromHob;\r
+ BOOLEAN FromHob;\r
\r
//\r
// Prevent notification being interrupted by debug timer\r
//\r
- BOOLEAN InNotify;\r
+ BOOLEAN InNotify;\r
\r
//\r
// PciIo protocol event\r
//\r
- EFI_PHYSICAL_ADDRESS PciIoEvent;\r
+ EFI_PHYSICAL_ADDRESS PciIoEvent;\r
\r
//\r
// The flag indicates if USB 3.0 ports has been turn off/on power\r
//\r
- BOOLEAN ChangePortPower;\r
+ BOOLEAN ChangePortPower;\r
\r
//\r
// XHCI MMIO Base address\r
//\r
- EFI_PHYSICAL_ADDRESS XhciMmioBase;\r
+ EFI_PHYSICAL_ADDRESS XhciMmioBase;\r
\r
//\r
// XHCI OP RegisterBase address\r
//\r
- EFI_PHYSICAL_ADDRESS XhciOpRegister;\r
+ EFI_PHYSICAL_ADDRESS XhciOpRegister;\r
\r
//\r
// XHCI Debug Register Base Address\r
//\r
- EFI_PHYSICAL_ADDRESS DebugCapabilityBase;\r
+ EFI_PHYSICAL_ADDRESS DebugCapabilityBase;\r
\r
//\r
// XHCI Debug Capability offset\r
//\r
- UINT64 DebugCapabilityOffset;\r
+ UINT64 DebugCapabilityOffset;\r
\r
//\r
// XHCI Debug Context Address\r
//\r
- EFI_PHYSICAL_ADDRESS DebugCapabilityContext;\r
+ EFI_PHYSICAL_ADDRESS DebugCapabilityContext;\r
\r
//\r
// Transfer Ring\r
//\r
- TRANSFER_RING TransferRingOut;\r
- TRANSFER_RING TransferRingIn;\r
+ TRANSFER_RING TransferRingOut;\r
+ TRANSFER_RING TransferRingIn;\r
\r
//\r
// EventRing\r
//\r
- EVENT_RING EventRing;\r
+ EVENT_RING EventRing;\r
\r
//\r
// URB - Read\r
//\r
- URB UrbOut;\r
+ URB UrbOut;\r
\r
//\r
// URB - Write\r
//\r
- URB UrbIn;\r
+ URB UrbIn;\r
\r
//\r
// The available data length in the following data buffer.\r
//\r
- UINT8 DataCount;\r
+ UINT8 DataCount;\r
//\r
// The data buffer address for data read and poll.\r
//\r
- EFI_PHYSICAL_ADDRESS Data;\r
+ EFI_PHYSICAL_ADDRESS Data;\r
} USB3_DEBUG_PORT_HANDLE;\r
\r
#pragma pack()\r
**/\r
UINT32\r
XhcReadDebugReg (\r
- IN USB3_DEBUG_PORT_HANDLE *Handle,\r
- IN UINT32 Offset\r
+ IN USB3_DEBUG_PORT_HANDLE *Handle,\r
+ IN UINT32 Offset\r
);\r
\r
/**\r
**/\r
VOID\r
XhcWriteDebugReg (\r
- IN USB3_DEBUG_PORT_HANDLE *Handle,\r
- IN UINT32 Offset,\r
- IN UINT32 Data\r
+ IN USB3_DEBUG_PORT_HANDLE *Handle,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Data\r
);\r
\r
/**\r
is not enabled.\r
**/\r
BOOLEAN\r
-XhcIsBitSet(\r
+XhcIsBitSet (\r
UINTN Register,\r
UINT32 BitMask\r
);\r
@param[in] BitMask 32-bit mask\r
**/\r
VOID\r
-XhcSetR32Bit(\r
+XhcSetR32Bit (\r
UINTN Register,\r
UINT32 BitMask\r
);\r
@param[in] BitMask 32-bit mask\r
**/\r
VOID\r
-XhcClearR32Bit(\r
- IN OUT UINTN Register,\r
- IN UINT32 BitMask\r
+XhcClearR32Bit (\r
+ IN OUT UINTN Register,\r
+ IN UINT32 BitMask\r
);\r
\r
/**\r
@return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
-VOID*\r
+VOID *\r
AllocateAlignBuffer (\r
- IN UINTN BufferSize\r
+ IN UINTN BufferSize\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcDataTransfer (\r
- IN USB3_DEBUG_PORT_HANDLE *Handle,\r
- IN EFI_USB_DATA_DIRECTION Direction,\r
- IN OUT VOID *Data,\r
- IN OUT UINTN *DataLength,\r
- IN UINTN Timeout\r
+ IN USB3_DEBUG_PORT_HANDLE *Handle,\r
+ IN EFI_USB_DATA_DIRECTION Direction,\r
+ IN OUT VOID *Data,\r
+ IN OUT UINTN *DataLength,\r
+ IN UINTN Timeout\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
InitializeUsbDebugHardware (\r
- IN USB3_DEBUG_PORT_HANDLE *Handle\r
+ IN USB3_DEBUG_PORT_HANDLE *Handle\r
);\r
\r
/**\r
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