+++ /dev/null
-/* $NetBSD: ia64_cpu.h,v 1.1 2006/04/07 14:21:18 cherry Exp $ */\r
-\r
-/*-\r
- * Copyright (c) 2000 Doug Rabson\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- * 1. Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND\r
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
- * SUCH DAMAGE.\r
- *\r
- * $FreeBSD$\r
- */\r
-\r
-#ifndef _MACHINE_IA64_CPU_H_\r
-#define _MACHINE_IA64_CPU_H_\r
-\r
-/*\r
- * Definition of PSR and IPSR bits.\r
- */\r
-#define IA64_PSR_BE 0x0000000000000002\r
-#define IA64_PSR_UP 0x0000000000000004\r
-#define IA64_PSR_AC 0x0000000000000008\r
-#define IA64_PSR_MFL 0x0000000000000010\r
-#define IA64_PSR_MFH 0x0000000000000020\r
-#define IA64_PSR_IC 0x0000000000002000\r
-#define IA64_PSR_I 0x0000000000004000\r
-#define IA64_PSR_PK 0x0000000000008000\r
-#define IA64_PSR_DT 0x0000000000020000\r
-#define IA64_PSR_DFL 0x0000000000040000\r
-#define IA64_PSR_DFH 0x0000000000080000\r
-#define IA64_PSR_SP 0x0000000000100000\r
-#define IA64_PSR_PP 0x0000000000200000\r
-#define IA64_PSR_DI 0x0000000000400000\r
-#define IA64_PSR_SI 0x0000000000800000\r
-#define IA64_PSR_DB 0x0000000001000000\r
-#define IA64_PSR_LP 0x0000000002000000\r
-#define IA64_PSR_TB 0x0000000004000000\r
-#define IA64_PSR_RT 0x0000000008000000\r
-#define IA64_PSR_CPL 0x0000000300000000\r
-#define IA64_PSR_CPL_KERN 0x0000000000000000\r
-#define IA64_PSR_CPL_1 0x0000000100000000\r
-#define IA64_PSR_CPL_2 0x0000000200000000\r
-#define IA64_PSR_CPL_USER 0x0000000300000000\r
-#define IA64_PSR_IS 0x0000000400000000\r
-#define IA64_PSR_MC 0x0000000800000000\r
-#define IA64_PSR_IT 0x0000001000000000\r
-#define IA64_PSR_ID 0x0000002000000000\r
-#define IA64_PSR_DA 0x0000004000000000\r
-#define IA64_PSR_DD 0x0000008000000000\r
-#define IA64_PSR_SS 0x0000010000000000\r
-#define IA64_PSR_RI 0x0000060000000000\r
-#define IA64_PSR_RI_0 0x0000000000000000\r
-#define IA64_PSR_RI_1 0x0000020000000000\r
-#define IA64_PSR_RI_2 0x0000040000000000\r
-#define IA64_PSR_ED 0x0000080000000000\r
-#define IA64_PSR_BN 0x0000100000000000\r
-#define IA64_PSR_IA 0x0000200000000000\r
-\r
-/*\r
- * Definition of ISR bits.\r
- */\r
-#define IA64_ISR_CODE 0x000000000000ffff\r
-#define IA64_ISR_VECTOR 0x0000000000ff0000\r
-#define IA64_ISR_X 0x0000000100000000\r
-#define IA64_ISR_W 0x0000000200000000\r
-#define IA64_ISR_R 0x0000000400000000\r
-#define IA64_ISR_NA 0x0000000800000000\r
-#define IA64_ISR_SP 0x0000001000000000\r
-#define IA64_ISR_RS 0x0000002000000000\r
-#define IA64_ISR_IR 0x0000004000000000\r
-#define IA64_ISR_NI 0x0000008000000000\r
-#define IA64_ISR_SO 0x0000010000000000\r
-#define IA64_ISR_EI 0x0000060000000000\r
-#define IA64_ISR_EI_0 0x0000000000000000\r
-#define IA64_ISR_EI_1 0x0000020000000000\r
-#define IA64_ISR_EI_2 0x0000040000000000\r
-#define IA64_ISR_ED 0x0000080000000000\r
-\r
-/*\r
- * Vector numbers for various ia64 interrupts.\r
- */\r
-#define IA64_VEC_VHPT 0\r
-#define IA64_VEC_ITLB 1\r
-#define IA64_VEC_DTLB 2\r
-#define IA64_VEC_ALT_ITLB 3\r
-#define IA64_VEC_ALT_DTLB 4\r
-#define IA64_VEC_NESTED_DTLB 5\r
-#define IA64_VEC_IKEY_MISS 6\r
-#define IA64_VEC_DKEY_MISS 7\r
-#define IA64_VEC_DIRTY_BIT 8\r
-#define IA64_VEC_INST_ACCESS 9\r
-#define IA64_VEC_DATA_ACCESS 10\r
-#define IA64_VEC_BREAK 11\r
-#define IA64_VEC_EXT_INTR 12\r
-#define IA64_VEC_PAGE_NOT_PRESENT 20\r
-#define IA64_VEC_KEY_PERMISSION 21\r
-#define IA64_VEC_INST_ACCESS_RIGHTS 22\r
-#define IA64_VEC_DATA_ACCESS_RIGHTS 23\r
-#define IA64_VEC_GENERAL_EXCEPTION 24\r
-#define IA64_VEC_DISABLED_FP 25\r
-#define IA64_VEC_NAT_CONSUMPTION 26\r
-#define IA64_VEC_SPECULATION 27\r
-#define IA64_VEC_DEBUG 29\r
-#define IA64_VEC_UNALIGNED_REFERENCE 30\r
-#define IA64_VEC_UNSUPP_DATA_REFERENCE 31\r
-#define IA64_VEC_FLOATING_POINT_FAULT 32\r
-#define IA64_VEC_FLOATING_POINT_TRAP 33\r
-#define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34\r
-#define IA64_VEC_TAKEN_BRANCH_TRAP 35\r
-#define IA64_VEC_SINGLE_STEP_TRAP 36\r
-#define IA64_VEC_IA32_EXCEPTION 45\r
-#define IA64_VEC_IA32_INTERCEPT 46\r
-#define IA64_VEC_IA32_INTERRUPT 47\r
-\r
-/*\r
- * IA-32 exceptions.\r
- */\r
-#define IA32_EXCEPTION_DIVIDE 0\r
-#define IA32_EXCEPTION_DEBUG 1\r
-#define IA32_EXCEPTION_BREAK 3\r
-#define IA32_EXCEPTION_OVERFLOW 4\r
-#define IA32_EXCEPTION_BOUND 5\r
-#define IA32_EXCEPTION_DNA 7\r
-#define IA32_EXCEPTION_NOT_PRESENT 11\r
-#define IA32_EXCEPTION_STACK_FAULT 12\r
-#define IA32_EXCEPTION_GPFAULT 13\r
-#define IA32_EXCEPTION_FPERROR 16\r
-#define IA32_EXCEPTION_ALIGNMENT_CHECK 17\r
-#define IA32_EXCEPTION_STREAMING_SIMD 19\r
-\r
-#define IA32_INTERCEPT_INSTRUCTION 0\r
-#define IA32_INTERCEPT_GATE 1\r
-#define IA32_INTERCEPT_SYSTEM_FLAG 2\r
-#define IA32_INTERCEPT_LOCK 4\r
-\r
-#ifndef _LOCORE\r
-\r
-/*\r
- * Various special ia64 instructions.\r
- */\r
-\r
-/*\r
- * Memory Fence.\r
- */\r
-static __inline void\r
-ia64_mf(void)\r
-{\r
- __asm __volatile("mf");\r
-}\r
-\r
-static __inline void\r
-ia64_mf_a(void)\r
-{\r
- __asm __volatile("mf.a");\r
-}\r
-\r
-/*\r
- * Flush Cache.\r
- */\r
-static __inline void\r
-ia64_fc(u_int64_t va)\r
-{\r
- __asm __volatile("fc %0" :: "r"(va));\r
-}\r
-\r
-/* \r
- * Flush Instruction Cache\r
- */\r
-\r
-static __inline void\r
-ia64_fc_i(u_int64_t va)\r
-{\r
- __asm __volatile("fc.i %0" :: "r"(va));\r
-}\r
-\r
-/*\r
- * Sync instruction stream.\r
- */\r
-static __inline void\r
-ia64_sync_i(void)\r
-{\r
- __asm __volatile("sync.i");\r
-}\r
-\r
-/*\r
- * Calculate address in VHPT for va.\r
- */\r
-static __inline u_int64_t\r
-ia64_thash(u_int64_t va)\r
-{\r
- u_int64_t result;\r
- __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));\r
- return result;\r
-}\r
-\r
-/*\r
- * Calculate VHPT tag for va.\r
- */\r
-static __inline u_int64_t\r
-ia64_ttag(u_int64_t va)\r
-{\r
- u_int64_t result;\r
- __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));\r
- return result;\r
-}\r
-\r
-/*\r
- * Convert virtual address to physical.\r
- */\r
-static __inline u_int64_t\r
-ia64_tpa(u_int64_t va)\r
-{\r
- u_int64_t result;\r
- __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));\r
- return result;\r
-}\r
-\r
-/*\r
- * Generate a ptc.e instruction.\r
- */\r
-static __inline void\r
-ia64_ptc_e(u_int64_t v)\r
-{\r
- __asm __volatile("ptc.e %0;; srlz.d;;" :: "r"(v));\r
-}\r
-\r
-/*\r
- * Generate a ptc.g instruction.\r
- */\r
-static __inline void\r
-ia64_ptc_g(u_int64_t va, u_int64_t log2size)\r
-{\r
- __asm __volatile("ptc.g %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size));\r
-}\r
-\r
-/*\r
- * Generate a ptc.ga instruction.\r
- */\r
-static __inline void\r
-ia64_ptc_ga(u_int64_t va, u_int64_t log2size)\r
-{\r
- __asm __volatile("ptc.ga %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size));\r
-}\r
-\r
-/*\r
- * Generate a ptc.l instruction.\r
- */\r
-static __inline void\r
-ia64_ptc_l(u_int64_t va, u_int64_t log2size)\r
-{\r
- __asm __volatile("ptc.l %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size));\r
-}\r
-\r
-/*\r
- * Read the value of psr.\r
- */\r
-static __inline u_int64_t\r
-ia64_get_psr(void)\r
-{\r
- u_int64_t result;\r
- __asm __volatile("mov %0=psr;;" : "=r" (result));\r
- return result;\r
-}\r
-\r
-/*\r
- * Define accessors for application registers.\r
- */\r
-\r
-#define IA64_AR(name) \\r
- \\r
-static __inline u_int64_t \\r
-ia64_get_##name(void) \\r
-{ \\r
- u_int64_t result; \\r
- __asm __volatile("mov %0=ar." #name : "=r" (result)); \\r
- return result; \\r
-} \\r
- \\r
-static __inline void \\r
-ia64_set_##name(u_int64_t v) \\r
-{ \\r
- __asm __volatile("mov ar." #name "=%0;;" :: "r" (v)); \\r
-}\r
-\r
-IA64_AR(k0)\r
-IA64_AR(k1)\r
-IA64_AR(k2)\r
-IA64_AR(k3)\r
-IA64_AR(k4)\r
-IA64_AR(k5)\r
-IA64_AR(k6)\r
-IA64_AR(k7)\r
-\r
-IA64_AR(rsc)\r
-IA64_AR(bsp)\r
-IA64_AR(bspstore)\r
-IA64_AR(rnat)\r
-\r
-IA64_AR(fcr)\r
-\r
-IA64_AR(eflag)\r
-IA64_AR(csd)\r
-IA64_AR(ssd)\r
-IA64_AR(cflg)\r
-IA64_AR(fsr)\r
-IA64_AR(fir)\r
-IA64_AR(fdr)\r
-\r
-IA64_AR(ccv)\r
-\r
-IA64_AR(unat)\r
-\r
-IA64_AR(fpsr)\r
-\r
-IA64_AR(itc)\r
-\r
-IA64_AR(pfs)\r
-IA64_AR(lc)\r
-IA64_AR(ec)\r
-\r
-/*\r
- * Define accessors for control registers.\r
- */\r
-\r
-#define IA64_CR(name) \\r
- \\r
-static __inline u_int64_t \\r
-ia64_get_##name(void) \\r
-{ \\r
- u_int64_t result; \\r
- __asm __volatile("mov %0=cr." #name : "=r" (result)); \\r
- return result; \\r
-} \\r
- \\r
-static __inline void \\r
-ia64_set_##name(u_int64_t v) \\r
-{ \\r
- __asm __volatile("mov cr." #name "=%0;;" :: "r" (v)); \\r
-}\r
-\r
-IA64_CR(dcr)\r
-IA64_CR(itm)\r
-IA64_CR(iva)\r
-\r
-IA64_CR(pta)\r
-\r
-IA64_CR(ipsr)\r
-IA64_CR(isr)\r
-\r
-IA64_CR(iip)\r
-IA64_CR(ifa)\r
-IA64_CR(itir)\r
-IA64_CR(iipa)\r
-IA64_CR(ifs)\r
-IA64_CR(iim)\r
-IA64_CR(iha)\r
-\r
-IA64_CR(lid)\r
-IA64_CR(ivr)\r
-IA64_CR(tpr)\r
-IA64_CR(eoi)\r
-IA64_CR(irr0)\r
-IA64_CR(irr1)\r
-IA64_CR(irr2)\r
-IA64_CR(irr3)\r
-IA64_CR(itv)\r
-IA64_CR(pmv)\r
-IA64_CR(cmcv)\r
-\r
-IA64_CR(lrr0)\r
-IA64_CR(lrr1)\r
-\r
-/*\r
- * Write a region register.\r
- */\r
-static __inline void\r
-ia64_set_rr(u_int64_t rrbase, u_int64_t v)\r
-{\r
- __asm __volatile("mov rr[%0]=%1;; srlz.d;;"\r
- :: "r"(rrbase), "r"(v) : "memory");\r
-}\r
-\r
-/*\r
- * Read a CPUID register.\r
- */\r
-static __inline u_int64_t\r
-ia64_get_cpuid(int i)\r
-{\r
- u_int64_t result;\r
- __asm __volatile("mov %0=cpuid[%1]"\r
- : "=r" (result) : "r"(i));\r
- return result;\r
-}\r
-\r
-static __inline void\r
-ia64_disable_highfp(void)\r
-{\r
- __asm __volatile("ssm psr.dfh;; srlz.d");\r
-}\r
-\r
-static __inline void\r
-ia64_enable_highfp(void)\r
-{\r
- __asm __volatile("rsm psr.dfh;; srlz.d");\r
-}\r
-\r
-#endif /* !_LOCORE */\r
-\r
-#endif /* _MACHINE_IA64_CPU_H_ */\r
-\r
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