Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r
PRINT_BIT_FIELD (Ebx, FSGSBASE);\r
PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);\r
+ PRINT_BIT_FIELD (Ebx, SGX);\r
PRINT_BIT_FIELD (Ebx, BMI1);\r
PRINT_BIT_FIELD (Ebx, HLE);\r
PRINT_BIT_FIELD (Ebx, AVX2);\r
PRINT_BIT_FIELD (Ecx, PKU);\r
PRINT_BIT_FIELD (Ecx, OSPKE);\r
}\r
- SubLeaf++;\r
- } while (SubLeaf <= Eax);\r
+ }\r
}\r
\r
/**\r
CpuidPlatformQosEnforcementResidSubLeaf ();\r
}\r
\r
+/**\r
+ Display Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
+\r
+**/\r
+VOID\r
+CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (\r
+ VOID\r
+ )\r
+{\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);\r
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
+ PRINT_BIT_FIELD (Eax, SGX1);\r
+ PRINT_BIT_FIELD (Eax, SGX2);\r
+ PRINT_BIT_FIELD (Edx, MaxEnclaveSize_Not64);\r
+ PRINT_BIT_FIELD (Edx, MaxEnclaveSize_64);\r
+}\r
+\r
+/**\r
+ Display Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
+\r
+**/\r
+VOID\r
+CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
+ &Eax, &Ebx, &Ecx, &Edx\r
+ );\r
+ Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);\r
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r
+}\r
+\r
+/**\r
+ Display Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
+\r
+**/\r
+VOID\r
+CpuidEnumerationOfIntelSgxResourcesSubLeaf (\r
+ VOID\r
+ )\r
+{\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
+ UINT32 SubLeaf;\r
+ \r
+ SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;\r
+ do {\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, SubLeaf,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ if (Eax.Bits.SubLeafType == 0x1) {\r
+ Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);\r
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
+ PRINT_BIT_FIELD (Eax, SubLeafType);\r
+ PRINT_BIT_FIELD (Eax, LowAddressOfEpcSection);\r
+ PRINT_BIT_FIELD (Ebx, HighAddressOfEpcSection);\r
+ PRINT_BIT_FIELD (Ecx, EpcSection);\r
+ PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);\r
+ PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);\r
+ }\r
+ SubLeaf++;\r
+ } while (Eax.Bits.SubLeafType == 0x1);\r
+}\r
+\r
+/**\r
+ Display Intel SGX Resource Enumeration.\r
+\r
+**/\r
+VOID\r
+CpuidEnumerationOfIntelSgx (\r
+ VOID\r
+ )\r
+{\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
+\r
+ if (CPUID_INTEL_SGX > gMaximumBasicFunction) {\r
+ return;\r
+ }\r
+\r
+ AsmCpuidEx (\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
+ NULL, &Ebx.Uint32, NULL, NULL\r
+ );\r
+ if (Ebx.Bits.SGX != 1) {\r
+ //\r
+ // Only if CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor has support\r
+ // for Intel SGX.\r
+ //\r
+ return;\r
+ }\r
+ \r
+ CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ();\r
+ CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ();\r
+ CpuidEnumerationOfIntelSgxResourcesSubLeaf ();\r
+}\r
+\r
/**\r
Display CPUID_INTEL_PROCESSOR_TRACE sub-leafs.\r
\r
CpuidPlatformQosMonitoringEnumerationSubLeaf ();\r
CpuidPlatformQosMonitoringCapabilitySubLeaf ();\r
CpuidPlatformQosEnforcementMainLeaf ();\r
+ CpuidEnumerationOfIntelSgx ();\r
CpuidIntelProcessorTraceMainLeaf ();\r
CpuidTimeStampCounter ();\r
CpuidProcessorFrequency ();\r