C based implemention of IA32 interrupt handling only\r
requiring a minimal assembly interrupt entry point.\r
\r
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "CpuDxe.h"\r
-\r
-\r
-//\r
-// Local structure definitions\r
-//\r
-\r
-#pragma pack (1)\r
-\r
-//\r
-// Global Descriptor Entry structures\r
-//\r
-\r
-typedef struct _GDT_ENTRY {\r
- UINT16 Limit15_0;\r
- UINT16 Base15_0;\r
- UINT8 Base23_16;\r
- UINT8 Type;\r
- UINT8 Limit19_16_and_flags;\r
- UINT8 Base31_24;\r
-} GDT_ENTRY;\r
-\r
-typedef\r
-struct _GDT_ENTRIES {\r
- GDT_ENTRY Null;\r
- GDT_ENTRY Linear;\r
- GDT_ENTRY LinearCode;\r
- GDT_ENTRY SysData;\r
- GDT_ENTRY SysCode;\r
- GDT_ENTRY LinearCode64;\r
- GDT_ENTRY Spare4;\r
- GDT_ENTRY Spare5;\r
-} GDT_ENTRIES;\r
-\r
-#define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null)\r
-#define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear)\r
-#define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode)\r
-#define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData)\r
-#define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode)\r
-#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)\r
-#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4)\r
-#define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5)\r
-\r
-#if defined (MDE_CPU_IA32)\r
-#define CPU_CODE_SEL LINEAR_CODE_SEL\r
-#define CPU_DATA_SEL LINEAR_SEL\r
-#elif defined (MDE_CPU_X64)\r
-#define CPU_CODE_SEL LINEAR_CODE64_SEL\r
-#define CPU_DATA_SEL LINEAR_SEL\r
-#else\r
-#error CPU type not supported for CPU GDT initialization!\r
-#endif\r
+#include "CpuGdt.h"\r
\r
//\r
// Global descriptor table (GDT) Template\r
// LINEAR_SEL\r
//\r
{\r
- 0x0FFFF, // limit 0xFFFFF\r
- 0x0, // base 0\r
- 0x0,\r
- 0x092, // present, ring 0, data, expand-up, writable\r
+ 0x0FFFF, // limit 15:0\r
+ 0x0, // base 15:0\r
+ 0x0, // base 23:16\r
+ 0x092, // present, ring 0, data, read/write\r
0x0CF, // page-granular, 32-bit\r
0x0,\r
},\r
// LINEAR_CODE_SEL\r
//\r
{\r
- 0x0FFFF, // limit 0xFFFFF\r
- 0x0, // base 0\r
- 0x0,\r
- 0x09A, // present, ring 0, data, expand-up, writable\r
+ 0x0FFFF, // limit 15:0\r
+ 0x0, // base 15:0\r
+ 0x0, // base 23:16\r
+ 0x09F, // present, ring 0, code, execute/read, conforming, accessed\r
0x0CF, // page-granular, 32-bit\r
0x0,\r
},\r
// SYS_DATA_SEL\r
//\r
{\r
- 0x0FFFF, // limit 0xFFFFF\r
- 0x0, // base 0\r
- 0x0,\r
- 0x092, // present, ring 0, data, expand-up, writable\r
+ 0x0FFFF, // limit 15:0\r
+ 0x0, // base 15:0\r
+ 0x0, // base 23:16\r
+ 0x093, // present, ring 0, data, read/write, accessed\r
0x0CF, // page-granular, 32-bit\r
0x0,\r
},\r
// SYS_CODE_SEL\r
//\r
{\r
- 0x0FFFF, // limit 0xFFFFF\r
- 0x0, // base 0\r
- 0x0,\r
- 0x09A, // present, ring 0, data, expand-up, writable\r
+ 0x0FFFF, // limit 15:0\r
+ 0x0, // base 15:0\r
+ 0x0, // base 23:16\r
+ 0x09A, // present, ring 0, code, execute/read\r
0x0CF, // page-granular, 32-bit\r
0x0,\r
},\r
//\r
- // LINEAR_CODE64_SEL\r
+ // SPARE4_SEL\r
//\r
{\r
- 0x0FFFF, // limit 0xFFFFF\r
- 0x0, // base 0\r
- 0x0,\r
- 0x09B, // present, ring 0, code, expand-up, writable\r
- 0x0AF, // LimitHigh (CS.L=1, CS.D=0)\r
- 0x0, // base (high)\r
+ 0x0, // limit 15:0\r
+ 0x0, // base 15:0\r
+ 0x0, // base 23:16\r
+ 0x0, // type\r
+ 0x0, // limit 19:16, flags\r
+ 0x0, // base 31:24\r
},\r
//\r
- // SPARE4_SEL\r
+ // LINEAR_DATA64_SEL\r
//\r
{\r
- 0x0, // limit 0\r
- 0x0, // base 0\r
- 0x0,\r
- 0x0, // present, ring 0, data, expand-up, writable\r
- 0x0, // page-granular, 32-bit\r
+ 0x0FFFF, // limit 15:0\r
+ 0x0, // base 15:0\r
+ 0x0, // base 23:16\r
+ 0x092, // present, ring 0, data, read/write\r
+ 0x0CF, // page-granular, 32-bit\r
0x0,\r
},\r
//\r
+ // LINEAR_CODE64_SEL\r
+ //\r
+ {\r
+ 0x0FFFF, // limit 15:0\r
+ 0x0, // base 15:0\r
+ 0x0, // base 23:16\r
+ 0x09A, // present, ring 0, code, execute/read\r
+ 0x0AF, // page-granular, 64-bit code\r
+ 0x0, // base (high)\r
+ },\r
+ //\r
// SPARE5_SEL\r
//\r
{\r
- 0x0, // limit 0\r
- 0x0, // base 0\r
- 0x0,\r
- 0x0, // present, ring 0, data, expand-up, writable\r
- 0x0, // page-granular, 32-bit\r
- 0x0,\r
+ 0x0, // limit 15:0\r
+ 0x0, // base 15:0\r
+ 0x0, // base 23:16\r
+ 0x0, // type\r
+ 0x0, // limit 19:16, flags\r
+ 0x0, // base 31:24\r
},\r
};\r
\r
// Write GDT register\r
//\r
gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;\r
- gdtPtr.Limit = sizeof (GdtTemplate) - 1;\r
+ gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);\r
AsmWriteGdtr (&gdtPtr);\r
\r
//\r
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