--- /dev/null
+/** @file\r
+ Produces the CPU I/O 2 Protocol.\r
+\r
+Copyright (c) 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CpuIo2Dxe.h"\r
+\r
+EFI_HANDLE mHandle = NULL;\r
+EFI_CPU_IO2_PROTOCOL mCpuIo = {\r
+ {\r
+ CpuMemoryServiceRead,\r
+ CpuMemoryServiceWrite\r
+ },\r
+ {\r
+ CpuIoServiceRead,\r
+ CpuIoServiceWrite\r
+ }\r
+};\r
+\r
+/**\r
+ Worker function to check the validation of parameters for CPU I/O interface functions.\r
+\r
+ This function check the validation of parameters for CPU I/O interface functions.\r
+\r
+ @param Width Width of the Mmio/Io operation\r
+ @param Address Base address of the Mmio/Io operation\r
+ @param Count Count of the number of accesses to perform\r
+ @param Buffer Pointer to the buffer to read from memory\r
+ @param Limit Maximum address supported\r
+\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL\r
+ @retval EFI_UNSUPPORTED The address range specified by Width, Address and Count is invalid\r
+ @retval EFI_UNSUPPORTED The memory buffer is not aligned\r
+ @retval EFI_SUCCESS Parameters are valid\r
+\r
+**/\r
+EFI_STATUS\r
+CpuIoCheckParameter (\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer,\r
+ IN UINT64 Limit\r
+ )\r
+{\r
+ UINTN AlignMask;\r
+\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Address > Limit) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // For FiFo type, the target address won't increase during the access,\r
+ // so treat count as 1\r
+ //\r
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+ Count = 1;\r
+ }\r
+\r
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ if (Address - 1 + (UINT32)(1 << Width) * Count > Limit) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AlignMask = (1 << Width) - 1;\r
+ if ((UINTN) Buffer & AlignMask) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Worker function to update access width and count for access to the unaligned address.\r
+ Unaligned Io/MmIo address access, break up the request into word by word or byte by byte.\r
+\r
+ @param Address Base address of the Mmio/Io operation\r
+ @param PtrWidth Pointer to width of the Mmio/Io operation\r
+ Out, this value will be updated for access to the unaligned address.\r
+ @param PtrCount Pointer to count of the number of accesses to perform\r
+ Out, this value will be updated for access to the unaligned address.\r
+**/\r
+VOID\r
+CpuIoUpdateWidthCount (\r
+ IN UINT64 Address,\r
+ IN OUT EFI_CPU_IO_PROTOCOL_WIDTH *PtrWidth,\r
+ IN OUT UINTN *PtrCount\r
+ )\r
+{\r
+ EFI_CPU_IO_PROTOCOL_WIDTH BufferWidth;\r
+ UINTN BufferCount;\r
+\r
+ BufferWidth = *PtrWidth;\r
+ BufferCount = *PtrCount;\r
+ \r
+ switch (BufferWidth) {\r
+ case EfiCpuIoWidthUint8:\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint16:\r
+ if ((Address & 0x01) == 0) {\r
+ break;\r
+ } else {\r
+ BufferCount = BufferCount * 2;\r
+ BufferWidth = EfiCpuIoWidthUint8;\r
+ }\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint32:\r
+ if ((Address & 0x03) == 0) {\r
+ break;\r
+ } else if ((Address & 0x01) == 0) {\r
+ BufferCount = BufferCount * 2;\r
+ BufferWidth = EfiCpuIoWidthUint16;\r
+ } else {\r
+ BufferCount = BufferCount * 4;\r
+ BufferWidth = EfiCpuIoWidthUint8;\r
+ }\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint64:\r
+ if ((Address & 0x07) == 0) {\r
+ break;\r
+ } else if ((Address & 0x03) == 0) {\r
+ BufferCount = BufferCount * 2;\r
+ BufferWidth = EfiCpuIoWidthUint32;\r
+ } else if ((Address & 0x01) == 0) {\r
+ BufferCount = BufferCount * 4;\r
+ BufferWidth = EfiCpuIoWidthUint16;\r
+ } else {\r
+ BufferCount = BufferCount * 8;\r
+ BufferWidth = EfiCpuIoWidthUint8;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ return;\r
+ }\r
+\r
+ *PtrWidth = BufferWidth;\r
+ *PtrCount = BufferCount;\r
+\r
+ return;\r
+}\r
+\r
+/**\r
+ Worker function to perform memory mapped I/O read/write\r
+\r
+ This function provides private services to perform memory mapped I/O read/write.\r
+\r
+ @param Width Width of the memory mapped I/O operation\r
+ @param Count Count of the number of accesses to perform\r
+ @param DestinationStrideFlag Boolean flag indicates if the destination is to be incremented\r
+ @param Destination Destination of the memory mapped I/O operation\r
+ @param SourceStrideFlag Boolean flag indicates if the source is to be incremented\r
+ @param Source Source of the memory mapped I/O operation\r
+\r
+ @retval EFI_SUCCESS Successful operation\r
+ @retval EFI_INVALID_PARAMETER Width is invalid\r
+\r
+**/\r
+EFI_STATUS\r
+CpuIoMemRW (\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINTN Count,\r
+ IN BOOLEAN DestinationStrideFlag,\r
+ OUT PTR Destination,\r
+ IN BOOLEAN SourceStrideFlag,\r
+ IN PTR Source\r
+ )\r
+{\r
+ UINTN Stride;\r
+ UINTN DestinationStride;\r
+ UINTN SourceStride;\r
+\r
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ Stride = (UINT32)(1 << Width);\r
+ DestinationStride = DestinationStrideFlag ? Stride : 0;\r
+ SourceStride = SourceStrideFlag ? Stride : 0;\r
+\r
+ //\r
+ // Loop for each iteration and move the data\r
+ //\r
+ switch (Width) {\r
+ case EfiCpuIoWidthUint8:\r
+ for (; Count > 0; Count--, Destination.Buf += DestinationStride, Source.Buf += SourceStride) {\r
+ MmioWrite8((UINTN)Destination.Ui8 , MmioRead8((UINTN)Source.Ui8));\r
+ }\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint16:\r
+ for (; Count > 0; Count--, Destination.Buf += DestinationStride, Source.Buf += SourceStride) {\r
+ MmioWrite16((UINTN)Destination.Ui16 , MmioRead16((UINTN)Source.Ui16));\r
+ }\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint32:\r
+ for (; Count > 0; Count--, Destination.Buf += DestinationStride, Source.Buf += SourceStride) {\r
+ MmioWrite32((UINTN)Destination.Ui32 , MmioRead32((UINTN)Source.Ui32));\r
+ }\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint64:\r
+ for (; Count > 0; Count--, Destination.Buf += DestinationStride, Source.Buf += SourceStride) {\r
+ MmioWrite64((UINTN)Destination.Ui64 , MmioRead64((UINTN)Source.Ui64));\r
+ }\r
+ break;\r
+\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Enables a driver to read memory-mapped registers in the PI System memory space.\r
+\r
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the memory operation.\r
+ @param[in] Address The base address of the memory operation.\r
+ @param[in] Count The number of memory operations to perform. The number of bytes moved\r
+ is Width size * Count, starting at Address.\r
+ @param[out] Buffer The destination buffer to store the results.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the EFI system.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this EFI system. Or Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
+ Or,The address range specified by Address, Width, and Count is not valid for this EFI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuMemoryServiceRead (\r
+ IN EFI_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ PTR Source;\r
+ PTR Destination;\r
+ EFI_STATUS Status;\r
+ EFI_CPU_IO_PROTOCOL_WIDTH BufferWidth;\r
+\r
+ Status = CpuIoCheckParameter (Width, Address, Count, Buffer, MAX_ADDRESS);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Destination.Buf = Buffer;\r
+ Source.Buf = (VOID *) (UINTN) Address;\r
+ \r
+ //\r
+ // Support access to unaligned mmio address.\r
+ // Break up the request into byte by byte\r
+ //\r
+ BufferWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ CpuIoUpdateWidthCount (Address, &BufferWidth, &Count);\r
+\r
+ if (Width >= EfiCpuIoWidthUint8 && Width <= EfiCpuIoWidthUint64) {\r
+ return CpuIoMemRW (BufferWidth, Count, TRUE, Destination, TRUE, Source);\r
+ }\r
+\r
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+ return CpuIoMemRW (BufferWidth, Count, TRUE, Destination, FALSE, Source);\r
+ }\r
+\r
+ if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) {\r
+ return CpuIoMemRW (BufferWidth, Count, FALSE, Destination, TRUE, Source);\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+/**\r
+ Enables a driver to write memory-mapped registers in the PI System memory space.\r
+\r
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the memory operation.\r
+ @param[in] Address The base address of the memory operation.\r
+ @param[in] Count The number of memory operations to perform. The number of bytes moved\r
+ is Width size * Count, starting at Address.\r
+ @param[in] Buffer The source buffer from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the EFI system.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this EFI system. Or Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
+ Or,The address range specified by Address, Width, and Count is not valid for this EFI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuMemoryServiceWrite (\r
+ IN EFI_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ PTR Source;\r
+ PTR Destination;\r
+ EFI_STATUS Status;\r
+ EFI_CPU_IO_PROTOCOL_WIDTH BufferWidth;\r
+\r
+ Status = CpuIoCheckParameter (Width, Address, Count, Buffer, MAX_ADDRESS);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Destination.Buf = (VOID *) (UINTN) Address;\r
+ Source.Buf = Buffer;\r
+\r
+ //\r
+ // Support access to unaligned mmio address.\r
+ // Break up the request into byte by byte\r
+ //\r
+ BufferWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ CpuIoUpdateWidthCount (Address, &BufferWidth, &Count);\r
+\r
+ if (Width >= EfiCpuIoWidthUint8 && Width <= EfiCpuIoWidthUint64) {\r
+ return CpuIoMemRW (BufferWidth, Count, TRUE, Destination, TRUE, Source);\r
+ }\r
+\r
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+ return CpuIoMemRW (BufferWidth, Count, FALSE, Destination, TRUE, Source);\r
+ }\r
+\r
+ if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) {\r
+ return CpuIoMemRW (BufferWidth, Count, TRUE, Destination, FALSE, Source);\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+/**\r
+ Enables a driver to read registers in the PI CPU I/O space.\r
+\r
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible\r
+ for aligning the Address if required. \r
+ @param[in] Count The number of I/O operations to perform. The number of bytes moved\r
+ is Width size * Count, starting at Address.\r
+ @param[out] UserBuffer The destination buffer to store the results.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the EFI system.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this EFI system. Or Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
+ Or,The address range specified by Address, Width, and Count is not valid for this EFI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuIoServiceRead (\r
+ IN EFI_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ OUT VOID *UserBuffer\r
+ )\r
+{\r
+ UINTN InStride;\r
+ UINTN OutStride;\r
+ UINTN Address;\r
+ PTR Buffer;\r
+ EFI_STATUS Status;\r
+ EFI_CPU_IO_PROTOCOL_WIDTH BufferWidth; \r
+\r
+ Buffer.Buf = (UINT8 *) UserBuffer;\r
+\r
+ if (Width >= EfiCpuIoWidthMaximum) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Status = CpuIoCheckParameter (Width, UserAddress, Count, UserBuffer, IA32_MAX_IO_ADDRESS);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Support access to unaligned IO address.\r
+ // Break up the request into byte by byte\r
+ //\r
+ BufferWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ CpuIoUpdateWidthCount (UserAddress, &BufferWidth, &Count);\r
+\r
+ Address = (UINTN) UserAddress;\r
+ InStride = (UINT32)(1 << (BufferWidth & 0x03));\r
+ OutStride = InStride;\r
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+ InStride = 0;\r
+ }\r
+\r
+ if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) {\r
+ OutStride = 0;\r
+ }\r
+\r
+ //\r
+ // Loop for each iteration and move the data\r
+ //\r
+ switch (BufferWidth) {\r
+ case EfiCpuIoWidthUint8:\r
+ for (; Count > 0; Count--, Buffer.Buf += OutStride, Address += InStride) {\r
+ *Buffer.Ui8 = IoRead8 (Address);\r
+ }\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint16:\r
+ for (; Count > 0; Count--, Buffer.Buf += OutStride, Address += InStride) {\r
+ *Buffer.Ui16 = IoRead16 (Address);\r
+ }\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint32:\r
+ for (; Count > 0; Count--, Buffer.Buf += OutStride, Address += InStride) {\r
+ *Buffer.Ui32 = IoRead32 (Address);\r
+ }\r
+ break;\r
+\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Enables a driver to write registers in the PI CPU I/O space.\r
+\r
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible\r
+ for aligning the Address if required. \r
+ @param[in] Count The number of I/O operations to perform. The number of bytes moved\r
+ is Width size * Count, starting at Address.\r
+ @param[in] UserBuffer The source buffer from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the EFI system.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this EFI system. Or Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
+ Or,The address range specified by Address, Width, and Count is not valid for this EFI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuIoServiceWrite (\r
+ IN EFI_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ IN VOID *UserBuffer\r
+ )\r
+{\r
+ UINTN InStride;\r
+ UINTN OutStride;\r
+ UINTN Address;\r
+ PTR Buffer;\r
+ EFI_STATUS Status;\r
+ EFI_CPU_IO_PROTOCOL_WIDTH BufferWidth;\r
+\r
+ Buffer.Buf = (UINT8 *) UserBuffer;\r
+\r
+ if (Width >= EfiCpuIoWidthMaximum) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Status = CpuIoCheckParameter (Width, UserAddress, Count, UserBuffer, IA32_MAX_IO_ADDRESS);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Support access to unaligned IO address.\r
+ // Break up the request into byte by byte\r
+ //\r
+ BufferWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ CpuIoUpdateWidthCount (UserAddress, &BufferWidth, &Count);\r
+\r
+ Address = (UINTN) UserAddress;\r
+ InStride = (UINT32)(1 << (BufferWidth & 0x03));\r
+ OutStride = InStride;\r
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+ InStride = 0;\r
+ }\r
+\r
+ if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) {\r
+ OutStride = 0;\r
+ }\r
+\r
+ //\r
+ // Loop for each iteration and move the data\r
+ //\r
+ switch (BufferWidth) {\r
+ case EfiCpuIoWidthUint8:\r
+ for (; Count > 0; Count--, Buffer.Buf += OutStride, Address += InStride) {\r
+ IoWrite8 (Address, *Buffer.Ui8);\r
+ }\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint16:\r
+ for (; Count > 0; Count--, Buffer.Buf += OutStride, Address += InStride) {\r
+ IoWrite16 (Address, *Buffer.Ui16);\r
+ }\r
+ break;\r
+\r
+ case EfiCpuIoWidthUint32:\r
+ for (; Count > 0; Count--, Buffer.Buf += OutStride, Address += InStride) {\r
+ IoWrite32 (Address, *Buffer.Ui32);\r
+ }\r
+ break;\r
+\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Entrypoint of CPU I/O 2 DXE module.\r
+ \r
+ @param ImageHandle The firmware allocated handle for the EFI image.\r
+ @param SystemTable A pointer to the EFI System Table.\r
+ \r
+ @retval EFI_SUCCESS The entry point is executed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuIo2Initialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = gBS->InstallProtocolInterface (\r
+ &mHandle,\r
+ &gEfiCpuIo2ProtocolGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ &mCpuIo\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
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