/** @file\r
Produces the CPU I/O 2 Protocol.\r
\r
-Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
//\r
// CPU I/O 2 Protocol instance\r
//\r
-EFI_CPU_IO2_PROTOCOL mCpuIo2 = {\r
+EFI_CPU_IO2_PROTOCOL mCpuIo2 = {\r
{\r
CpuMemoryServiceRead,\r
CpuMemoryServiceWrite\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
-UINT8 mInStride[] = {\r
+UINT8 mInStride[] = {\r
1, // EfiCpuIoWidthUint8\r
2, // EfiCpuIoWidthUint16\r
4, // EfiCpuIoWidthUint32\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
-UINT8 mOutStride[] = {\r
+UINT8 mOutStride[] = {\r
1, // EfiCpuIoWidthUint8\r
2, // EfiCpuIoWidthUint16\r
4, // EfiCpuIoWidthUint32\r
/**\r
Check parameters to a CPU I/O 2 Protocol service request.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
+\r
@param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[in] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
// For FIFO type, the target address won't increase during the access,\r
// so treat Count as 1\r
//\r
- if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+ if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {\r
Count = 1;\r
}\r
\r
//\r
// Check to see if Width is in the valid range for I/O Port operations\r
//\r
- Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
// Check to see if Address is aligned\r
//\r
- if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {\r
+ if ((Address & ((UINT64)mInStride[Width] - 1)) != 0) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
//\r
- // Check to see if any address associated with this transfer exceeds the maximum \r
+ // Check to see if any address associated with this transfer exceeds the maximum\r
// allowed address. The maximum address implied by the parameters passed in is\r
// Address + Size * Count. If the following condition is met, then the transfer\r
// is not supported.\r
//\r
// Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1\r
//\r
- // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count \r
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count\r
// can also be the maximum integer value supported by the CPU, this range\r
// check must be adjusted to avoid all oveflow conditions.\r
- // \r
- // The following form of the range check is equivalent but assumes that \r
+ //\r
+ // The following form of the range check is equivalent but assumes that\r
// MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).\r
//\r
Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);\r
if (Address > Limit) {\r
return EFI_UNSUPPORTED;\r
}\r
- } else { \r
+ } else {\r
MaxCount = RShiftU64 (Limit, Width);\r
if (MaxCount < (Count - 1)) {\r
return EFI_UNSUPPORTED;\r
}\r
+\r
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
return EFI_UNSUPPORTED;\r
}\r
/**\r
Reads memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[out] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
*Uint8Buffer = MmioRead8 ((UINTN)Address);\r
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
Writes memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[in] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
Reads I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[out] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
+\r
+ //\r
+ // Fifo operations supported for (mInStride[Width] == 0)\r
+ //\r
+ if (InStride == 0) {\r
+ switch (OperationWidth) {\r
+ case EfiCpuIoWidthUint8:\r
+ IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint16:\r
+ IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint32:\r
+ IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The CpuIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ }\r
+\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
*Uint8Buffer = IoRead8 ((UINTN)Address);\r
/**\r
Write I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[in] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
+\r
+ //\r
+ // Fifo operations supported for (mInStride[Width] == 0)\r
+ //\r
+ if (InStride == 0) {\r
+ switch (OperationWidth) {\r
+ case EfiCpuIoWidthUint8:\r
+ IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint16:\r
+ IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint32:\r
+ IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The CpuIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ }\r
+\r
for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
IoWrite8 ((UINTN)Address, *Uint8Buffer);\r
IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
}\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
The user Entry Point for module CpuIo2Dxe. The user code starts with this function.\r
\r
- @param[in] ImageHandle The firmware allocated handle for the EFI image. \r
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
@param[in] SystemTable A pointer to the EFI System Table.\r
- \r
+\r
@retval EFI_SUCCESS The entry point is executed successfully.\r
@retval other Some error occurs when executing this entry point.\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&mHandle,\r
- &gEfiCpuIo2ProtocolGuid, &mCpuIo2,\r
+ &gEfiCpuIo2ProtocolGuid,\r
+ &mCpuIo2,\r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r
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