};\r
\r
\r
-/**\r
- Get CPU Package/Core/Thread location information.\r
-\r
- @param InitialApicId CPU APIC ID\r
- @param Location Pointer to CPU location information\r
-**/\r
-STATIC\r
-VOID\r
-ExtractProcessorLocation (\r
- IN UINT32 InitialApicId,\r
- OUT EFI_CPU_PHYSICAL_LOCATION *Location\r
- )\r
-{\r
- BOOLEAN TopologyLeafSupported;\r
- UINTN ThreadBits;\r
- UINTN CoreBits;\r
- UINT32 RegEax;\r
- UINT32 RegEbx;\r
- UINT32 RegEcx;\r
- UINT32 RegEdx;\r
- UINT32 MaxCpuIdIndex;\r
- UINT32 SubIndex;\r
- UINTN LevelType;\r
- UINT32 MaxLogicProcessorsPerPackage;\r
- UINT32 MaxCoresPerPackage;\r
-\r
- //\r
- // Check if the processor is capable of supporting more than one logical processor.\r
- //\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);\r
- if ((RegEdx & BIT28) == 0) {\r
- Location->Thread = 0;\r
- Location->Core = 0;\r
- Location->Package = 0;\r
- return;\r
- }\r
-\r
- ThreadBits = 0;\r
- CoreBits = 0;\r
-\r
- //\r
- // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
- //\r
-\r
- TopologyLeafSupported = FALSE;\r
- //\r
- // Get the max index of basic CPUID\r
- //\r
- AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
-\r
- //\r
- // If the extended topology enumeration leaf is available, it\r
- // is the preferred mechanism for enumerating topology.\r
- //\r
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
- AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);\r
- //\r
- // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
- // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
- // supported on that processor.\r
- //\r
- if (RegEbx != 0) {\r
- TopologyLeafSupported = TRUE;\r
-\r
- //\r
- // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
- // the SMT sub-field of x2APIC ID.\r
- //\r
- LevelType = (RegEcx >> 8) & 0xff;\r
- ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
- ThreadBits = RegEax & 0x1f;\r
-\r
- //\r
- // Software must not assume any "level type" encoding\r
- // value to be related to any sub-leaf index, except sub-leaf 0.\r
- //\r
- SubIndex = 1;\r
- do {\r
- AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);\r
- LevelType = (RegEcx >> 8) & 0xff;\r
- if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
- CoreBits = (RegEax & 0x1f) - ThreadBits;\r
- break;\r
- }\r
- SubIndex++;\r
- } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
- }\r
- }\r
-\r
- if (!TopologyLeafSupported) {\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
- MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;\r
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
- AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);\r
- MaxCoresPerPackage = (RegEax >> 26) + 1;\r
- } else {\r
- //\r
- // Must be a single-core processor.\r
- //\r
- MaxCoresPerPackage = 1;\r
- }\r
-\r
- ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
- CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r
- }\r
-\r
- Location->Thread = InitialApicId & ~((-1) << ThreadBits);\r
- Location->Core = (InitialApicId >> ThreadBits) & ~((-1) << CoreBits);\r
- Location->Package = (InitialApicId >> (ThreadBits + CoreBits));\r
-}\r
-\r
-/**\r
- Worker function for SwitchBSP().\r
-\r
- Worker function for SwitchBSP(), assigned to the AP which is intended to become BSP.\r
-\r
- @param Buffer Pointer to CPU MP Data\r
-**/\r
-STATIC\r
-VOID\r
-EFIAPI\r
-FutureBSPProc (\r
- IN VOID *Buffer\r
- )\r
-{\r
- PEI_CPU_MP_DATA *DataInHob;\r
-\r
- DataInHob = (PEI_CPU_MP_DATA *) Buffer;\r
- AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo);\r
-}\r
-\r
/**\r
This service retrieves the number of logical processor in the platform\r
and the number of those logical processors that are enabled on this boot.\r