-;------------------------------------------------------------------------------ ;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-; This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php.
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-; Module Name:
-;
-; MpFuncs32.asm
-;
-; Abstract:
-;
-; This is the assembly code for MP support
-;
-;-------------------------------------------------------------------------------
-
-include MpEqu.inc
-.code
-
-
-AsmInitializeGdt PROC
- push rbp
- mov rbp, rsp
-
- lgdt fword PTR [rcx] ; update the GDTR
-
- sub rsp, 0x10
- lea rax, SetCodeSelectorFarJump
- mov [rsp], rax
- mov rdx, LONG_MODE_CS
- mov [rsp + 4], dx ; get new CS
- jmp fword ptr [rsp]
-SetCodeSelectorFarJump:
- add rsp, 0x10
-
- mov rax, LONG_MODE_DS ; get new DS
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-
- pop rbp
- ret
-AsmInitializeGdt ENDP
-
-END
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; MpFuncs32.asm\r
+;\r
+; Abstract:\r
+;\r
+; This is the assembly code for MP support\r
+;\r
+;-------------------------------------------------------------------------------\r
+\r
+include MpEqu.inc\r
+extern InitializeFloatingPointUnits:PROC\r
+\r
+.code\r
+;-------------------------------------------------------------------------------------\r
+;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
+;procedure serializes all the AP processors through an Init sequence. It must be\r
+;noted that APs arrive here very raw...ie: real mode, no stack.\r
+;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
+;IS IN MACHINE CODE.\r
+;-------------------------------------------------------------------------------------\r
+RendezvousFunnelProc PROC PUBLIC\r
+RendezvousFunnelProcStart::\r
+; At this point CS = 0x(vv00) and ip= 0x0.\r
+; Save BIST information to ebp firstly\r
+ db 66h, 08bh, 0e8h ; mov ebp, eax ; save BIST information\r
+\r
+ db 8ch,0c8h ; mov ax, cs\r
+ db 8eh,0d8h ; mov ds, ax\r
+ db 8eh,0c0h ; mov es, ax\r
+ db 8eh,0d0h ; mov ss, ax\r
+ db 33h,0c0h ; xor ax, ax\r
+ db 8eh,0e0h ; mov fs, ax\r
+ db 8eh,0e8h ; mov gs, ax\r
+\r
+ db 0BEh ; opcode of mov si, mem16\r
+ dw BufferStartLocation ; mov si, BufferStartLocation\r
+ db 66h, 8Bh, 1Ch ; mov ebx, dword ptr [si]\r
+\r
+ db 0BFh ; opcode of mov di, mem16 \r
+ dw LmodeOffsetLocation ; mov di, LmodeOffsetLocation\r
+ db 66h, 8Bh, 05h ; mov eax, [di]\r
+ db 0BFh ; opcode of mov di, mem16 \r
+ dw CodeSegmentLocation ; mov di, CodeSegmentLocation\r
+ db 66h, 8Bh, 15h ; mov edx, [di]\r
+ db 89h, 0C7h ; mov di, ax\r
+ db 83h, 0EFh, 02h ; sub di, 02h \r
+ db 89h, 15h ; mov [di], dx ; Patch long mode CS\r
+ db 83h, 0EFh, 04h ; sub di, 04h\r
+ db 66h, 01h, 0D8h ; add eax, ebx\r
+ db 66h, 89h, 05h ; mov [di], eax ; Patch address\r
+\r
+ db 0BEh ; opcode of mov si, mem16\r
+ dw GdtrLocation ; mov si, GdtrLocation\r
+ db 66h ; db 66h\r
+ db 2Eh, 0Fh, 01h, 14h ; lgdt fword ptr cs:[si]\r
+\r
+ db 0BEh\r
+ dw IdtrLocation ; mov si, IdtrLocation\r
+ db 66h ; db 66h\r
+ db 2Eh,0Fh, 01h, 1Ch ; lidt fword ptr cs:[si]\r
+\r
+ db 0BFh ; opcode of mov di, mem16 \r
+ dw DataSegmentLocation ; mov di, DataSegmentLocation\r
+ db 66h, 8Bh, 3Dh ; mov edi, [di] ; Save long mode DS in edi\r
+\r
+ db 0BEh\r
+ dw Cr3Location ; mov si, Cr3Location\r
+ db 66h, 8Bh, 0Ch ; mov ecx, dword ptr [si] ; ECX is keeping the value of CR3\r
+\r
+ db 31h, 0C0h ; xor ax, ax\r
+ db 8Eh, 0D8h ; mov ds, ax ; Clear data segment\r
+\r
+ db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Get control register 0\r
+ db 66h, 83h, 0C8h, 03h ; or eax, 000000003h ; Set PE bit (bit #0) & MP\r
+ db 0Fh, 22h, 0C0h ; mov cr0, eax\r
+\r
+ db 0Fh, 20h, 0E0h ; mov eax, cr4\r
+ db 66h, 0Fh, 0BAh, 0E8h, 05h ; bts eax, 5\r
+ db 0Fh, 22h, 0E0h ; mov cr4, eax\r
+\r
+ db 0Fh, 22h, 0D9h ; mov cr3, ecx\r
+\r
+ db 66h, 0B9h\r
+ dd 0C0000080h ; mov ecx, 0c0000080h ; EFER MSR number.\r
+ db 0Fh, 32h ; rdmsr ; Read EFER.\r
+ db 66h, 0Fh, 0BAh, 0E8h, 08h; bts eax, 8 ; Set LME=1.\r
+ db 0Fh, 30h ; wrmsr ; Write EFER.\r
+\r
+ db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Read CR0.\r
+ db 66h, 0Fh, 0BAh, 0E8h, 1Fh; bts eax, 31 ; Set PG=1.\r
+ db 0Fh, 22h, 0C0h ; mov cr0, eax ; Write CR0.\r
+\r
+LONG_JUMP:\r
+ db 66h, 0EAh ; far jump\r
+ dd 0h ; 32-bit offset\r
+ dw 0h ; 16-bit selector\r
+\r
+LongModeStart::\r
+ mov eax, edi\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov ss, ax\r
+\r
+ mov esi, ebx\r
+ mov edi, esi\r
+ add edi, LockLocation\r
+ mov rax, NotVacantFlag\r
+\r
+TestLock:\r
+ xchg qword ptr [edi], rax\r
+ cmp rax, NotVacantFlag\r
+ jz TestLock\r
+\r
+ mov edi, esi\r
+ add edi, NumApsExecutingLoction\r
+ inc dword ptr [edi]\r
+ mov ebx, dword ptr [edi]\r
+\r
+ProgramStack:\r
+ mov edi, esi\r
+ add edi, StackSizeLocation\r
+ mov rax, qword ptr [edi]\r
+ mov edi, esi\r
+ add edi, StackStartAddressLocation\r
+ add rax, qword ptr [edi]\r
+ mov rsp, rax\r
+ mov qword ptr [edi], rax\r
+\r
+Releaselock:\r
+ mov rax, VacantFlag\r
+ mov edi, esi\r
+ add edi, LockLocation\r
+ xchg qword ptr [edi], rax\r
+\r
+CProcedureInvoke:\r
+ push rbp ; push BIST data\r
+ xor rbp, rbp ; clear ebp for call stack trace\r
+ push rbp\r
+ mov rbp, rsp\r
+\r
+ mov rax, InitializeFloatingPointUnits\r
+ sub rsp, 20h\r
+ call rax ; Call assembly function to initialize FPU per UEFI spec\r
+ add rsp, 20h\r
+\r
+ mov edx, ebx ; edx is NumApsExecuting\r
+ mov ecx, esi\r
+ add ecx, LockLocation ; rcx is address of exchange info data buffer\r
+\r
+ mov edi, esi\r
+ add edi, ApProcedureLocation\r
+ mov rax, qword ptr [edi]\r
+\r
+ sub rsp, 20h\r
+ call rax ; invoke C function\r
+ add rsp, 20h\r
+ jmp $\r
+\r
+RendezvousFunnelProc ENDP\r
+RendezvousFunnelProcEnd::\r
+\r
+;-------------------------------------------------------------------------------------\r
+; AsmGetAddressMap (&AddressMap);\r
+;-------------------------------------------------------------------------------------\r
+AsmGetAddressMap PROC\r
+ mov rax, offset RendezvousFunnelProcStart\r
+ mov qword ptr [rcx], rax\r
+ mov qword ptr [rcx + 8h], 0\r
+ mov qword ptr [rcx + 10h], LongModeStart - RendezvousFunnelProcStart\r
+ mov qword ptr [rcx + 18h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
+ ret\r
+AsmGetAddressMap ENDP\r
+\r
+;-------------------------------------------------------------------------------------\r
+;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
+;about to become an AP. It switches it'stack with the current AP.\r
+;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);\r
+;-------------------------------------------------------------------------------------\r
+AsmExchangeRole PROC\r
+ ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
+ ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
+\r
+ push rax\r
+ push rbx\r
+ push rcx\r
+ push rdx\r
+ push rsi\r
+ push rdi\r
+ push rbp\r
+ push r8\r
+ push r9\r
+ push r10\r
+ push r11\r
+ push r12\r
+ push r13\r
+ push r14\r
+ push r15\r
+\r
+ mov rax, cr0\r
+ push rax\r
+\r
+ mov rax, cr4\r
+ push rax\r
+\r
+ ; rsi contains MyInfo pointer\r
+ mov rsi, rcx\r
+\r
+ ; rdi contains OthersInfo pointer\r
+ mov rdi, rdx\r
+\r
+ ;Store EFLAGS, GDTR and IDTR regiter to stack\r
+ pushfq\r
+ sgdt fword ptr [rsi + 16]\r
+ sidt fword ptr [rsi + 26]\r
+\r
+ ; Store the its StackPointer\r
+ mov qword ptr [rsi + 8], rsp\r
+\r
+ ; update its switch state to STORED\r
+ mov byte ptr [rsi], CPU_SWITCH_STATE_STORED\r
+\r
+WaitForOtherStored:\r
+ ; wait until the other CPU finish storing its state\r
+ cmp byte ptr [rdi], CPU_SWITCH_STATE_STORED\r
+ jz OtherStored\r
+ pause\r
+ jmp WaitForOtherStored\r
+\r
+OtherStored:\r
+ ; Since another CPU already stored its state, load them\r
+ ; load GDTR value\r
+ lgdt fword ptr [rdi + 16]\r
+\r
+ ; load IDTR value\r
+ lidt fword ptr [rdi + 26]\r
+\r
+ ; load its future StackPointer\r
+ mov rsp, qword ptr [rdi + 8]\r
+\r
+ ; update the other CPU's switch state to LOADED\r
+ mov byte ptr [rdi], CPU_SWITCH_STATE_LOADED\r
+\r
+WaitForOtherLoaded:\r
+ ; wait until the other CPU finish loading new state,\r
+ ; otherwise the data in stack may corrupt\r
+ cmp byte ptr [rsi], CPU_SWITCH_STATE_LOADED\r
+ jz OtherLoaded\r
+ pause\r
+ jmp WaitForOtherLoaded\r
+\r
+OtherLoaded:\r
+ ; since the other CPU already get the data it want, leave this procedure\r
+ popfq\r
+\r
+ pop rax\r
+ mov cr4, rax\r
+\r
+ pop rax\r
+ mov cr0, rax\r
+\r
+ pop r15\r
+ pop r14\r
+ pop r13\r
+ pop r12\r
+ pop r11\r
+ pop r10\r
+ pop r9\r
+ pop r8\r
+ pop rbp\r
+ pop rdi\r
+ pop rsi\r
+ pop rdx\r
+ pop rcx\r
+ pop rbx\r
+ pop rax\r
+\r
+ ret\r
+AsmExchangeRole ENDP\r
+\r
+END\r
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