+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;\r
+\r
+/**\r
+ L2 Cache Allocation Technology Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)\r
+\r
+ @retval EAX RESID L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.\r
+ @retval EBX Bit-granular map of isolation/contention of allocation units.\r
+ @retval ECX Reserved.\r
+ @retval EDX RESID L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r
+\r
+/**\r
+ CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
+ /// using minus-one notation.\r
+ ///\r
+ UINT32 CapacityLength:5;\r
+ UINT32 Reserved:27;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Highest COS number supported for this ResID.\r
+ ///\r
+ UINT32 HighestCosNumber:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ Intel SGX resource capability and configuration.\r
+ See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".\r
+\r
+ If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying\r
+ CPUID with EAX=12H on Intel SGX resource capability and configuration.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).\r
+ CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).\r
+ Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])\r
+ until the sub-leaf type is invalid.\r
+\r
+**/\r
+#define CPUID_INTEL_SGX 0x12\r
+\r
+/**\r
+ Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
+ Enumerates Intel SGX capability, including enclave instruction opcode support.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)\r
+\r
+ @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
+ described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.\r
+ @retval EBX MISCSELECT: Reports the bit vector of supported extended features\r
+ that can be written to the MISC region of the SSA.\r
+ @retval ECX Reserved.\r
+ @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
+ described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r
+\r
+/**\r
+ Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,\r
+ sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.\r
+ ///\r
+ UINT32 SGX1:1;\r
+ ///\r
+ /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r
+ ///\r
+ UINT32 SGX2:1;\r
+ UINT32 Reserved:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;\r
+\r
+/**\r
+ Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,\r
+ sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes\r
+ /// when not in 64-bit mode.\r
+ ///\r
+ UINT32 MaxEnclaveSize_Not64:8;\r
+ ///\r
+ /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes\r
+ /// when operating in 64-bit mode.\r
+ ///\r
+ UINT32 MaxEnclaveSize_64:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
+ Enumerates Intel SGX capability of processor state configuration and enclave\r
+ configuration in the SECS structure.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)\r
+\r
+ @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE\r
+ only if EAX[n] is 1, where n < 32.\r
+ @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE\r
+ only if EBX[n] is 1, where n < 32.\r
+ @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE\r
+ only if ECX[n] is 1, where n < 32.\r
+ @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE\r
+ only if EDX[n] is 1, where n < 32.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
+ &Eax, &Ebx, &Ecx, &Edx\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r
+\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
+ Enumerates available EPC resources.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)\r
+\r
+ @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.\r
+ @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.\r
+ @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.\r
+ @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 3:0] Sub-leaf-type encoding.\r
+ /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.\r
+ /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)\r
+ /// in EBX:EAX and EDX:ECX.\r
+ /// All other encoding are reserved.\r
+ ///\r
+ UINT32 SubLeafType:4;\r
+ UINT32 Reserved:8;\r
+ ///\r
+ /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of\r
+ /// the base of the EPC section.\r
+ ///\r
+ UINT32 LowAddressOfEpcSection:20;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of\r
+ /// the base of the EPC section.\r
+ ///\r
+ UINT32 HighAddressOfEpcSection:20;\r
+ UINT32 Reserved:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 3:0] The EPC section encoding.\r
+ /// 0000b: Not valid.\r
+ /// 0001b: The EPC section is confidentiality, integrity and replay protected.\r
+ /// All other encoding are reserved.\r
+ ///\r
+ UINT32 EpcSection:4;\r
+ UINT32 Reserved:8;\r
+ ///\r
+ /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the\r
+ /// corresponding EPC section within the Processor Reserved Memory.\r
+ ///\r
+ UINT32 LowSizeOfEpcSection:20;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the\r
+ /// corresponding EPC section within the Processor Reserved Memory.\r
+ ///\r
+ UINT32 HighSizeOfEpcSection:20;\r
+ UINT32 Reserved:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;\r
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