+/**\r
+ CPUID Architectural Performance Monitoring\r
+\r
+ @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)\r
+\r
+ @retval EAX Architectural Performance Monitoring information described by\r
+ the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.\r
+ @retval EBX Architectural Performance Monitoring information described by\r
+ the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.\r
+ @retval ECX Reserved.\r
+ @retval EDX Architectural Performance Monitoring information described by\r
+ the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r
+ CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r
+ CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r
+\r
+ AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r
+ @endcode\r
+**/\r
+#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A\r
+\r
+/**\r
+ CPUID Architectural Performance Monitoring EAX for CPUID leaf\r
+ #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 7:0] Version ID of architectural performance monitoring.\r
+ ///\r
+ UINT32 ArchPerfMonVerID:8;\r
+ ///\r
+ /// [Bits 15:8] Number of general-purpose performance monitoring counter\r
+ /// per logical processor.\r
+ ///\r
+ /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous\r
+ /// block of MSR address space. Each performance event select register is\r
+ /// paired with a corresponding performance counter in the 0C1H address\r
+ /// block.\r
+ ///\r
+ UINT32 PerformanceMonitorCounters:8;\r
+ ///\r
+ /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.\r
+ ///\r
+ /// The bit width of an IA32_PMCx MSR. This the number of valid bits for\r
+ /// read operation. On write operations, the lower-order 32 bits of the MSR\r
+ /// may be written with any value, and the high-order bits are sign-extended\r
+ /// from the value of bit 31.\r
+ ///\r
+ UINT32 PerformanceMonitorCounterWidth:8;\r
+ ///\r
+ /// [Bits 31:24] Length of EBX bit vector to enumerate architectural\r
+ /// performance monitoring events.\r
+ ///\r
+ UINT32 EbxBitVectorLength:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;\r
+\r
+/**\r
+ CPUID Architectural Performance Monitoring EBX for CPUID leaf\r
+ #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core cycle event not available if 1.\r
+ ///\r
+ UINT32 UnhaltedCoreCycles:1;\r
+ ///\r
+ /// [Bit 1] Instruction retired event not available if 1.\r
+ ///\r
+ UINT32 InstructionsRetired:1;\r
+ ///\r
+ /// [Bit 2] Reference cycles event not available if 1.\r
+ ///\r
+ UINT32 UnhaltedReferenceCycles:1;\r
+ ///\r
+ /// [Bit 3] Last-level cache reference event not available if 1.\r
+ ///\r
+ UINT32 LastLevelCacheReferences:1;\r
+ ///\r
+ /// [Bit 4] Last-level cache misses event not available if 1.\r
+ ///\r
+ UINT32 LastLevelCacheMisses:1;\r
+ ///\r
+ /// [Bit 5] Branch instruction retired event not available if 1.\r
+ ///\r
+ UINT32 BranchInstructionsRetired:1;\r
+ ///\r
+ /// [Bit 6] Branch mispredict retired event not available if 1.\r
+ ///\r
+ UINT32 AllBranchMispredictRetired:1;\r
+ UINT32 Reserved:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;\r
+\r
+/**\r
+ CPUID Architectural Performance Monitoring EDX for CPUID leaf\r
+ #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Number of fixed-function performance counters\r
+ /// (if Version ID > 1).\r
+ ///\r
+ UINT32 FixedFunctionPerformanceCounters:5;\r
+ ///\r
+ /// [Bits 12:5] Bit width of fixed-function performance counters\r
+ /// (if Version ID > 1).\r
+ ///\r
+ UINT32 FixedFunctionPerformanceCounterWidth:8;\r
+ UINT32 Reserved:19;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;\r
+\r
+\r
+/**\r
+ CPUID Extended Topology Information\r
+\r
+ @note\r
+ Most of Leaf 0BH output depends on the initial value in ECX. The EDX output\r
+ of leaf 0BH is always valid and does not vary with input value in ECX. Output\r
+ value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that\r
+ return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If\r
+ an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],\r
+ other input values with ECX > n also return 0 in ECX[15:8].\r
+\r
+ @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)\r
+ @param ECX Level number\r
+\r
+ @retval EAX Extended topology information described by the type\r
+ CPUID_EXTENDED_TOPOLOGY_EAX.\r
+ @retval EBX Extended topology information described by the type\r
+ CPUID_EXTENDED_TOPOLOGY_EBX.\r
+ @retval ECX Extended topology information described by the type\r
+ CPUID_EXTENDED_TOPOLOGY_ECX.\r
+ @retval EDX x2APIC ID the current logical processor.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r
+ CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r
+ CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r
+ UINT32 Edx;\r
+ UINT32 LevelNumber;\r
+\r
+ LevelNumber = 0;\r
+ do {\r
+ AsmCpuidEx (\r
+ CPUID_EXTENDED_TOPOLOGY, LevelNumber,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r
+ );\r
+ LevelNumber++;\r
+ } while (Eax.Bits.ApicIdShift != 0);\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_TOPOLOGY 0x0B\r
+\r
+/**\r
+ CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique\r
+ /// topology ID of the next level type. All logical processors with the\r
+ /// same next level ID share current level.\r
+ ///\r
+ /// @note\r
+ /// Software should use this field (EAX[4:0]) to enumerate processor\r
+ /// topology of the system.\r
+ ///\r
+ UINT32 ApicIdShift:5;\r
+ UINT32 Reserved:27;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_TOPOLOGY_EAX;\r
+\r
+/**\r
+ CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Number of logical processors at this level type. The number\r
+ /// reflects configuration as shipped by Intel.\r
+ ///\r
+ /// @note\r
+ /// Software must not use EBX[15:0] to enumerate processor topology of the\r
+ /// system. This value in this field (EBX[15:0]) is only intended for\r
+ /// display/diagnostic purposes. The actual number of logical processors\r
+ /// available to BIOS/OS/Applications may be different from the value of\r
+ /// EBX[15:0], depending on software and platform hardware configurations.\r
+ ///\r
+ UINT32 LogicalProcessors:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_TOPOLOGY_EBX;\r
+\r
+/**\r
+ CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Level number. Same value in ECX input.\r
+ ///\r
+ UINT32 LevelNumber:8;\r
+ ///\r
+ /// [Bits 15:8] Level type.\r
+ ///\r
+ /// @note\r
+ /// The value of the "level type" field is not related to level numbers in\r
+ /// any way, higher "level type" values do not mean higher levels.\r
+ ///\r
+ UINT32 LevelType:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_TOPOLOGY_ECX;\r
+\r
+///\r
+/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r
+///\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r
+///\r
+/// @}\r
+///\r
+\r
+\r
+/**\r
+ CPUID Extended State Information\r
+\r
+ @param EAX CPUID_EXTENDED_STATE (0x0D)\r
+ @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).\r
+ CPUID_EXTENDED_STATE_SUB_LEAF (0x01).\r
+ CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).\r
+ Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.\r
+**/\r
+#define CPUID_EXTENDED_STATE 0x0D\r
+\r
+/**\r
+ CPUID Extended State Information Main Leaf\r
+\r
+ @param EAX CPUID_EXTENDED_STATE (0x0D)\r
+ @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)\r
+\r
+ @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]\r
+ can be set to 1 only if EAX[n] is 1. The format of the extended\r
+ state main leaf is described by the type\r
+ CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.\r
+ @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
+ area) required by enabled features in XCR0. May be different than\r
+ ECX if some features at the end of the XSAVE save area are not\r
+ enabled.\r
+ @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
+ area) of the XSAVE/XRSTOR save area required by all supported\r
+ features in the processor, i.e., all the valid bit fields in XCR0.\r
+ @retval EDX Reports the supported bits of the upper 32 bits of XCR0.\r
+ XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r
+ &Eax.Uint32, &Ebx, &Ecx, &Edx\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r
+\r
+/**\r
+ CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
+ sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] x87 state.\r
+ ///\r
+ UINT32 x87:1;\r
+ ///\r
+ /// [Bit 1] SSE state.\r
+ ///\r
+ UINT32 SSE:1;\r
+ ///\r
+ /// [Bit 2] AVX state.\r
+ ///\r
+ UINT32 AVX:1;\r
+ ///\r
+ /// [Bits 4:3] MPX state.\r
+ ///\r
+ UINT32 MPX:2;\r
+ ///\r
+ /// [Bits 7:5] AVX-512 state.\r
+ ///\r
+ UINT32 AVX_512:3;\r
+ ///\r
+ /// [Bit 8] Used for IA32_XSS.\r
+ ///\r
+ UINT32 IA32_XSS:1;\r
+ ///\r
+ /// [Bit 9] PKRU state.\r
+ ///\r
+ UINT32 PKRU:1;\r
+ UINT32 Reserved:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;\r
+\r
+/**\r
+ CPUID Extended State Information Sub Leaf\r
+\r
+ @param EAX CPUID_EXTENDED_STATE (0x0D)\r
+ @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)\r
+\r
+ @retval EAX The format of the extended state sub-leaf is described by the\r
+ type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.\r
+ @retval EBX The size in bytes of the XSAVE area containing all states\r
+ enabled by XCRO | IA32_XSS.\r
+ @retval ECX The format of the extended state sub-leaf is described by the\r
+ type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.\r
+ @retval EDX Reports the supported bits of the upper 32 bits of the\r
+ IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r
+\r
+/**\r
+ CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
+ sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] XSAVEOPT is available.\r
+ ///\r
+ UINT32 XSAVEOPT:1;\r
+ ///\r
+ /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.\r
+ ///\r
+ UINT32 XSAVEC:1;\r
+ ///\r
+ /// [Bit 2] Supports XGETBV with ECX = 1 if set.\r
+ ///\r
+ UINT32 XGETBV:1;\r
+ ///\r
+ /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.\r
+ ///\r
+ UINT32 XSAVES:1;\r
+ UINT32 Reserved:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
+ sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Used for XCR0.\r
+ ///\r
+ UINT32 XCR0:1;\r
+ ///\r
+ /// [Bit 8] PT STate.\r
+ ///\r
+ UINT32 PT:1;\r
+ ///\r
+ /// [Bit 9] Used for XCR0.\r
+ ///\r
+ UINT32 XCR0_1:1;\r
+ UINT32 Reserved:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;\r
+\r
+/**\r
+ CPUID Extended State Information Size and Offset Sub Leaf\r
+\r
+ @note\r
+ Leaf 0DH output depends on the initial value in ECX.\r
+ Each sub-leaf index (starting at position 2) is supported if it corresponds to\r
+ a supported bit in either the XCR0 register or the IA32_XSS MSR.\r
+ If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r
+ n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1\r
+ returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0\r
+ returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].\r
+\r
+ @param EAX CPUID_EXTENDED_STATE (0x0D)\r
+ @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based\r
+ on supported bits in XCR0 or IA32_XSS_MSR.\r
+\r
+ @retval EAX The size in bytes (from the offset specified in EBX) of the save\r
+ area for an extended state feature associated with a valid\r
+ sub-leaf index, n.\r
+ @retval EBX The offset in bytes of this extended state component's save area\r
+ from the beginning of the XSAVE/XRSTOR area. This field reports\r
+ 0 if the sub-leaf index, n, does not map to a valid bit in the\r
+ XCR0 register.\r
+ @retval ECX The format of the extended state components's save area as\r
+ described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.\r
+ This field reports 0 if the sub-leaf index, n, is invalid.\r
+ @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;\r
+ otherwise it is reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r
+ UINT32 Edx;\r
+ UINTN SubLeaf;\r
+\r
+ for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r
+ AsmCpuidEx (\r
+ CPUID_EXTENDED_STATE, SubLeaf,\r
+ &Eax, &Ebx, &Ecx.Uint32, &Edx\r
+ );\r
+ }\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r
+\r
+/**\r
+ CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
+ sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is\r
+ /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported\r
+ /// in XCR0.\r
+ ///\r
+ UINT32 XSS:1;\r
+ ///\r
+ /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,\r
+ /// this extended state component located on the next 64-byte boundary\r
+ /// following the preceding state component (otherwise, it is located\r
+ /// immediately following the preceding state component).\r
+ ///\r
+ UINT32 Compacted:1;\r
+ UINT32 Reserved:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;\r
+\r
+\r
+/**\r
+ CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
+\r
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
+ @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).\r
+\r
+**/\r
+#define CPUID_INTEL_RDT_MONITORING 0x0F\r
+\r
+/**\r
+ CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
+ Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
+ @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r
+\r
+ @retval EAX Reserved.\r
+ @retval EBX Maximum range (zero-based) of RMID within this physical\r
+ processor of all types.\r
+ @retval ECX Reserved.\r
+ @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by\r
+ the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
+ NULL, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
+\r
+/**\r
+ CPUID Intel RDT Monitoring Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
+ #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheRDT_M:1;\r
+ UINT32 Reserved2:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
+\r
+/**\r
+ CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
+ @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)\r
+\r
+ @retval EAX Reserved.\r
+ @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r
+ @retval ECX Maximum range (zero-based) of RMID of this resource type.\r
+ @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the\r
+ type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
+ NULL, &Ebx, &Ecx, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01\r
+\r
+/**\r
+ CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
+ #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Supports L3 occupancy monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheOccupancyMonitoring:1;\r
+ ///\r
+ /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheTotalBandwidthMonitoring:1;\r
+ ///\r
+ /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheLocalBandwidthMonitoring:1;\r
+ UINT32 Reserved:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ CPUID Intel Resource Director Technology (Intel RDT) Allocation Information\r
+\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).\r
+**/\r
+#define CPUID_INTEL_RDT_ALLOCATION 0x10\r
+\r
+/**\r
+ Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r
+\r
+ @retval EAX Reserved.\r
+ @retval EBX L3 and L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.\r
+ @retval ECX Reserved.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
+ NULL, &Ebx.Uint32, NULL, NULL\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00\r
+\r
+/**\r
+ CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Supports L3 Cache Allocation Technology if 1.\r
+ ///\r
+ UINT32 L3CacheAllocation:1;\r
+ ///\r
+ /// [Bit 2] Supports L2 Cache Allocation Technology if 1.\r
+ ///\r
+ UINT32 L2CacheAllocation:1;\r
+ UINT32 Reserved2:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;\r
+\r
+\r
+/**\r
+ L3 Cache Allocation Technology Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)\r
+\r
+ @retval EAX RESID L3 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.\r
+ @retval EBX Bit-granular map of isolation/contention of allocation units.\r
+ @retval ECX RESID L3 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.\r
+ @retval EDX RESID L3 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01\r
+\r
+/**\r
+ CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
+ /// using minus-one notation.\r
+ ///\r
+ UINT32 CapacityLength:5;\r
+ UINT32 Reserved:27;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Updates of COS should be infrequent if 1.\r
+ ///\r
+ UINT32 CosUpdatesInfrequent:1;\r
+ ///\r
+ /// [Bit 2] Code and Data Prioritization Technology supported if 1.\r
+ ///\r
+ UINT32 CodeDataPrioritization:1;\r
+ UINT32 Reserved2:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;\r
+\r
+/**\r
+ CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Highest COS number supported for this ResID.\r
+ ///\r
+ UINT32 HighestCosNumber:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;\r
+\r
+/**\r
+ L2 Cache Allocation Technology Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)\r
+\r
+ @retval EAX RESID L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.\r
+ @retval EBX Bit-granular map of isolation/contention of allocation units.\r
+ @retval ECX Reserved.\r
+ @retval EDX RESID L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r
+\r
+/**\r
+ CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
+ /// using minus-one notation.\r
+ ///\r
+ UINT32 CapacityLength:5;\r
+ UINT32 Reserved:27;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Highest COS number supported for this ResID.\r
+ ///\r
+ UINT32 HighestCosNumber:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ Intel SGX resource capability and configuration.\r
+ See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".\r
+\r
+ If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying\r
+ CPUID with EAX=12H on Intel SGX resource capability and configuration.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).\r
+ CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).\r
+ Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])\r
+ until the sub-leaf type is invalid.\r
+\r
+**/\r
+#define CPUID_INTEL_SGX 0x12\r
+\r
+/**\r
+ Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
+ Enumerates Intel SGX capability, including enclave instruction opcode support.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)\r
+\r
+ @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
+ described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.\r
+ @retval EBX MISCSELECT: Reports the bit vector of supported extended features\r
+ that can be written to the MISC region of the SSA.\r
+ @retval ECX Reserved.\r
+ @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
+ described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r
+\r
+/**\r
+ Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,\r
+ sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.\r
+ ///\r
+ UINT32 SGX1:1;\r
+ ///\r
+ /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r
+ ///\r
+ UINT32 SGX2:1;\r
+ UINT32 Reserved:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;\r
+\r
+/**\r
+ Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,\r
+ sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes\r
+ /// when not in 64-bit mode.\r
+ ///\r
+ UINT32 MaxEnclaveSize_Not64:8;\r
+ ///\r
+ /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes\r
+ /// when operating in 64-bit mode.\r
+ ///\r
+ UINT32 MaxEnclaveSize_64:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
+ Enumerates Intel SGX capability of processor state configuration and enclave\r
+ configuration in the SECS structure.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)\r
+\r
+ @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE\r
+ only if EAX[n] is 1, where n < 32.\r
+ @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE\r
+ only if EBX[n] is 1, where n < 32.\r
+ @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE\r
+ only if ECX[n] is 1, where n < 32.\r
+ @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE\r
+ only if EDX[n] is 1, where n < 32.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
+ &Eax, &Ebx, &Ecx, &Edx\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r
+\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
+ Enumerates available EPC resources.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)\r
+\r
+ @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.\r
+ @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.\r
+ @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.\r
+ @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 3:0] Sub-leaf-type encoding.\r
+ /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.\r
+ /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)\r
+ /// in EBX:EAX and EDX:ECX.\r
+ /// All other encoding are reserved.\r
+ ///\r
+ UINT32 SubLeafType:4;\r
+ UINT32 Reserved:8;\r
+ ///\r
+ /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of\r
+ /// the base of the EPC section.\r
+ ///\r
+ UINT32 LowAddressOfEpcSection:20;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of\r
+ /// the base of the EPC section.\r
+ ///\r
+ UINT32 HighAddressOfEpcSection:20;\r
+ UINT32 Reserved:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 3:0] The EPC section encoding.\r
+ /// 0000b: Not valid.\r
+ /// 0001b: The EPC section is confidentiality, integrity and replay protected.\r
+ /// All other encoding are reserved.\r
+ ///\r
+ UINT32 EpcSection:4;\r
+ UINT32 Reserved:8;\r
+ ///\r
+ /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the\r
+ /// corresponding EPC section within the Processor Reserved Memory.\r
+ ///\r
+ UINT32 LowSizeOfEpcSection:20;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the\r
+ /// corresponding EPC section within the Processor Reserved Memory.\r
+ ///\r
+ UINT32 HighSizeOfEpcSection:20;\r
+ UINT32 Reserved:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ CPUID Intel Processor Trace Information\r
+\r
+ @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)\r
+ @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).\r
+ CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).\r
+\r
+**/\r
+#define CPUID_INTEL_PROCESSOR_TRACE 0x14\r
+\r
+/**\r
+ CPUID Intel Processor Trace Information Main Leaf\r
+\r
+ @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r
+ @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)\r
+\r
+ @retval EAX Reports the maximum sub-leaf supported in leaf 14H.\r
+ @retval EBX Returns Intel processor trace information described by the\r
+ type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.\r
+ @retval ECX Returns Intel processor trace information described by the\r
+ type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r
+ CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
+ &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r
+\r
+/**\r
+ CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
+ sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
+ /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
+ ///\r
+ UINT32 Cr3Filter:1;\r
+ ///\r
+ /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate\r
+ /// Mode.\r
+ ///\r
+ UINT32 ConfigurablePsb:1;\r
+ ///\r
+ /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,\r
+ /// and preservation of Intel PT MSRs across warm reset.\r
+ ///\r
+ UINT32 IpTraceStopFiltering:1;\r
+ ///\r
+ /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of\r
+ /// COFI-based packets.\r
+ ///\r
+ UINT32 Mtc:1;\r
+ ///\r
+ /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set\r
+ /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE\r
+ /// can generate packets.\r
+ ///\r
+ UINT32 PTWrite:1;\r
+ ///\r
+ /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set\r
+ /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet\r
+ /// generation.\r
+ ///\r
+ UINT32 PowerEventTrace:1;\r
+ UINT32 Reserved:26;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;\r
+\r
+/**\r
+ CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
+ sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence\r
+ /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and\r
+ /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.\r
+ ///\r
+ UINT32 RTIT:1;\r
+ ///\r
+ /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to\r
+ /// the maximum allowed by the MaskOrTableOffset field of\r
+ /// IA32_RTIT_OUTPUT_MASK_PTRS.\r
+ ///\r
+ UINT32 ToPA:1;\r
+ ///\r
+ /// [Bit 2] If 1, indicates support of Single-Range Output scheme.\r
+ ///\r
+ UINT32 SingleRangeOutput:1;\r
+ ///\r
+ /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.\r
+ ///\r
+ UINT32 TraceTransportSubsystem:1;\r
+ UINT32 Reserved:27;\r
+ ///\r
+ /// [Bit 31] If 1, generated packets which contain IP payloads have LIP\r
+ /// values, which include the CS base component.\r
+ ///\r
+ UINT32 LIP:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;\r
+\r
+\r
+/**\r
+ CPUID Intel Processor Trace Information Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r
+ @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)\r
+\r
+ @retval EAX Returns Intel processor trace information described by the\r
+ type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.\r
+ @retval EBX Returns Intel processor trace information described by the\r
+ type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.\r
+ @retval ECX Reserved.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 MaximumSubLeaf;\r
+ UINT32 SubLeaf;\r
+ CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
+ &MaximumSubLeaf, NULL, NULL, NULL\r
+ );\r
+\r
+ for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r
+ &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r
+ );\r
+ }\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r
+\r
+/**\r
+ CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
+ sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Number of configurable Address Ranges for filtering.\r
+ ///\r
+ UINT32 ConfigurableAddressRanges:3;\r
+ UINT32 Reserved:13;\r
+ ///\r
+ /// [Bits 31:16] Bitmap of supported MTC period encodings\r
+ ///\r
+ UINT32 MtcPeriodEncodings:16;\r
+\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
+ sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.\r
+ ///\r
+ UINT32 CycleThresholdEncodings:16;\r
+ ///\r
+ /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.\r
+ ///\r
+ UINT32 PsbFrequencyEncodings:16;\r
+\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;\r
+\r
+\r
+/**\r
+ CPUID Time Stamp Counter and Nominal Core Crystal Clock Information\r
+\r
+ @note\r
+ If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r
+ EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r
+ crystal clock frequency.\r
+ If ECX is 0, the nominal core crystal clock frequency is not enumerated.\r
+ "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r
+ The core crystal clock may differ from the reference clock, bus clock, or core\r
+ clock frequencies.\r
+\r
+ @param EAX CPUID_TIME_STAMP_COUNTER (0x15)\r
+\r
+ @retval EAX An unsigned integer which is the denominator of the\r
+ TSC/"core crystal clock" ratio\r
+ @retval EBX An unsigned integer which is the numerator of the\r
+ TSC/"core crystal clock" ratio.\r
+ @retval ECX An unsigned integer which is the nominal frequency\r
+ of the core crystal clock in Hz.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+\r
+ AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r
+ @endcode\r
+**/\r
+#define CPUID_TIME_STAMP_COUNTER 0x15\r
+\r
+\r
+/**\r
+ CPUID Processor Frequency Information\r
+\r
+ @note\r
+ Data is returned from this interface in accordance with the processor's\r
+ specification and does not reflect actual values. Suitable use of this data\r
+ includes the display of processor information in like manner to the processor\r
+ brand string and for determining the appropriate range to use when displaying\r
+ processor information e.g. frequency history graphs. The returned information\r
+ should not be used for any other purpose as the returned information does not\r
+ accurately correlate to information / counters returned by other processor\r
+ interfaces. While a processor may support the Processor Frequency Information\r
+ leaf, fields that return a value of zero are not supported.\r
+\r
+ @param EAX CPUID_TIME_STAMP_COUNTER (0x16)\r
+\r
+ @retval EAX Returns processor base frequency information described by the\r
+ type CPUID_PROCESSOR_FREQUENCY_EAX.\r
+ @retval EBX Returns maximum frequency information described by the type\r
+ CPUID_PROCESSOR_FREQUENCY_EBX.\r
+ @retval ECX Returns bus frequency information described by the type\r
+ CPUID_PROCESSOR_FREQUENCY_ECX.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r
+ CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r
+ CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r
+\r
+ AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
+ @endcode\r
+**/\r
+#define CPUID_PROCESSOR_FREQUENCY 0x16\r
+\r
+/**\r
+ CPUID Processor Frequency Information EAX for CPUID leaf\r
+ #CPUID_PROCESSOR_FREQUENCY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Processor Base Frequency (in MHz).\r
+ ///\r
+ UINT32 ProcessorBaseFrequency:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PROCESSOR_FREQUENCY_EAX;\r
+\r
+/**\r
+ CPUID Processor Frequency Information EBX for CPUID leaf\r
+ #CPUID_PROCESSOR_FREQUENCY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Maximum Frequency (in MHz).\r
+ ///\r
+ UINT32 MaximumFrequency:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PROCESSOR_FREQUENCY_EBX;\r
+\r
+/**\r
+ CPUID Processor Frequency Information ECX for CPUID leaf\r
+ #CPUID_PROCESSOR_FREQUENCY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Bus (Reference) Frequency (in MHz).\r
+ ///\r
+ UINT32 BusFrequency:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PROCESSOR_FREQUENCY_ECX;\r
+\r
+\r
+/**\r
+ CPUID SoC Vendor Information\r
+\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r
+ CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r
+ CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)\r
+ CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)\r
+\r
+ @note\r
+ Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String\r
+ is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC\r
+ Vendor Brand String is constructed by concatenating in ascending order of\r
+ EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.\r
+\r
+**/\r
+#define CPUID_SOC_VENDOR 0x17\r
+\r
+/**\r
+ CPUID SoC Vendor Information\r
+\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r
+\r
+ @retval EAX MaxSOCID_Index. Reports the maximum input value of supported\r
+ sub-leaf in leaf 17H.\r
+ @retval EBX Returns SoC Vendor information described by the type\r
+ CPUID_SOC_VENDOR_MAIN_LEAF_EBX.\r
+ @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC\r
+ projects.\r
+ @retval EDX Stepping ID. A unique number within an SOC project that an SOC\r
+ vendor assigns.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r
+ &Eax, &Ebx.Uint32, &Ecx, &Edx\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r
+\r
+/**\r
+ CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf\r
+ #CPUID_SOC_VENDOR_MAIN_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] SOC Vendor ID.\r
+ ///\r
+ UINT32 SocVendorId:16;\r
+ ///\r
+ /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry\r
+ /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is\r
+ /// assigned by Intel.\r
+ ///\r
+ UINT32 IsVendorScheme:1;\r
+ UINT32 Reserved:15;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;\r
+\r
+/**\r
+ CPUID SoC Vendor Information\r
+\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r
+\r
+ @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r
+\r
+/**\r
+ CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,\r
+ #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// 4 UTF-8 characters of Soc Vendor Brand String\r
+ ///\r
+ CHAR8 BrandString[4];\r
+ ///\r
+ /// All fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_SOC_VENDOR_BRAND_STRING_DATA;\r
+\r
+/**\r
+ CPUID SoC Vendor Information\r
+\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)\r
+\r
+ @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r
+\r
+/**\r
+ CPUID SoC Vendor Information\r
+\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)\r
+\r
+ @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r
+\r
+\r
+/**\r
+ CPUID Extended Function\r
+\r
+ @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)\r
+\r
+ @retval EAX Maximum Input Value for Extended Function CPUID Information.\r
+ @retval EBX Reserved.\r
+ @retval ECX Reserved.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+\r
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
+ @endcode\r
+**/\r