--- /dev/null
+/** @file\r
+ IA32 Local APIC Definitions.\r
+\r
+ Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __LOCAL_APIC_H__\r
+#define __LOCAL_APIC_H__\r
+\r
+//\r
+// Definitions for IA32 architectural MSRs\r
+//\r
+#define MSR_IA32_APIC_BASE_ADDRESS 0x1B\r
+\r
+//\r
+// Definitions for CPUID instruction\r
+//\r
+#define CPUID_VERSION_INFO 0x1\r
+#define CPUID_EXTENDED_FUNCTION 0x80000000\r
+#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
+\r
+//\r
+// Definition for Local APIC registers and related values\r
+//\r
+#define XAPIC_ID_OFFSET 0x0\r
+#define XAPIC_EOI_OFFSET 0x0b0\r
+#define XAPIC_ICR_DFR_OFFSET 0x0e0\r
+#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r
+#define XAPIC_ICR_LOW_OFFSET 0x300\r
+#define XAPIC_ICR_HIGH_OFFSET 0x310\r
+#define XAPIC_LVT_TIMER_OFFSET 0x320\r
+#define XAPIC_LINT0_VECTOR_OFFSET 0x350\r
+#define XAPIC_LINT1_VECTOR_OFFSET 0x360\r
+#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r
+#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r
+#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
+\r
+#define X2APIC_MSR_BASE_ADDRESS 0x800\r
+#define X2APIC_MSR_ICR_ADDRESS 0x830\r
+\r
+#define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r
+#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r
+#define LOCAL_APIC_DELIVERY_MODE_SMI 2\r
+#define LOCAL_APIC_DELIVERY_MODE_NMI 4\r
+#define LOCAL_APIC_DELIVERY_MODE_INIT 5\r
+#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r
+#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r
+\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
+\r
+typedef union {\r
+ struct {\r
+ UINT64 Reserved0:8; ///< Reserved.\r
+ UINT64 Bsp:1; ///< Processor is BSP.\r
+ UINT64 Reserved1:1; ///< Reserved.\r
+ UINT64 Extd:1; ///< Enable x2APIC mode.\r
+ UINT64 En:1; ///< xAPIC global enable/disable.\r
+ UINT64 ApicBase:52; ///< APIC Base physical address. The actual field width depends on physical address width.\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} MSR_IA32_APIC_BASE;\r
+\r
+//\r
+// Low half of Interrupt Command Register (ICR).\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
+ UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.\r
+ UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.\r
+ UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
+ UINT32 Reserved0:1; ///< Reserved.\r
+ UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
+ UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
+ UINT32 Reserved1:2; ///< Reserved.\r
+ UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.\r
+ UINT32 Reserved2:12; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_ICR_LOW;\r
+\r
+//\r
+// High half of Interrupt Command Register (ICR)\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Reserved0:24; ///< Reserved.\r
+ UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.\r
+ } Bits;\r
+ UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.\r
+} LOCAL_APIC_ICR_HIGH;\r
+\r
+//\r
+// Spurious-Interrupt Vector Register (SVR)\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 SpuriousVector:8; ///< Spurious Vector.\r
+ UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.\r
+ UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.\r
+ UINT32 Reserved0:2; ///< Reserved.\r
+ UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.\r
+ UINT32 Reserved1:19; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_SVR;\r
+\r
+//\r
+// Divide Configuration Register (DCR)\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.\r
+ UINT32 Reserved0:1; ///< Always 0.\r
+ UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.\r
+ UINT32 Reserved1:28; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_DCR;\r
+\r
+//\r
+// LVT Timer Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
+ UINT32 Reserved0:4; ///< Reserved.\r
+ UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
+ UINT32 Reserved1:3; ///< Reserved.\r
+ UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
+ UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.\r
+ UINT32 Reserved2:14; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_LVT_TIMER;\r
+\r
+//\r
+// LVT LINT0/LINT1 Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
+ UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
+ UINT32 Reserved0:1; ///< Reserved.\r
+ UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
+ UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.\r
+ UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
+ UINT32 TriggerMode:1; ///< 0:edge, 1:level.\r
+ UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
+ UINT32 Reserved1:15; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_LVT_LINT;\r
+\r
+#endif\r
+\r
projects / mirror_edk2.git / blobdiff