UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions

[mirror_edk2.git] / UefiCpuPkg / Include / Register / LocalApic.h

diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h
index 346cce675643062d137adc2da9dba533d6ce317e..cfb6d76d8b3449244e9c92e790c70dae7d9bd709 100644 (file)
--- a/UefiCpuPkg/Include/Register/LocalApic.h
+++ b/UefiCpuPkg/Include/Register/LocalApic.h
@@ -1,7 +1,7 @@
 /** @file\r
   IA32 Local APIC Definitions.\r
 \r
-  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -15,11 +15,6 @@
 #ifndef __LOCAL_APIC_H__\r
 #define __LOCAL_APIC_H__\r
 \r
-//\r
-// Definitions for IA32 architectural MSRs\r
-//\r
-#define MSR_IA32_APIC_BASE_ADDRESS              0x1B\r
-\r
 //\r
 // Definition for Local APIC registers and related values\r
 //\r
@@ -53,19 +48,6 @@
 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
 \r
-typedef union {\r
-  struct {\r
-    UINT32  Reserved0:8;     ///< Reserved.\r
-    UINT32  Bsp:1;           ///< Processor is BSP.\r
-    UINT32  Reserved1:1;     ///< Reserved.\r
-    UINT32  Extd:1;          ///< Enable x2APIC mode.\r
-    UINT32  En:1;            ///< xAPIC global enable/disable.\r
-    UINT32  ApicBaseLow:20;  ///< APIC Base physical address. The actual field width depends on physical address width.\r
-    UINT32  ApicBaseHigh:32;\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} MSR_IA32_APIC_BASE;\r
-\r
 //\r
 // Local APIC Version Register.\r
 //\r