returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
+ Is Intel processors based on the Broadwell microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x3D || \\r
+ DisplayModel == 0x47 || \\r
+ DisplayModel == 0x4F || \\r
+ DisplayModel == 0x56 \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
Facilities.".\r
\r
- @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
@param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;\r
+ MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
\r
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
@endcode\r
+ @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
- MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS\r
+ MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
///\r
UINT32 Ovf_FixedCtr2:1;\r
UINT32 Reserved2:20;\r
///\r
- /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical\r
+ /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
/// Addresses (ToPA).".\r
///\r
UINT32 Trace_ToPA_PMI:1;\r
/// All bit fields as a 64-bit value\r
///\r
UINT64 Uint64;\r
-} MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;\r
+} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
\r
/**\r
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
@endcode\r
+ @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r
\r
UINT64 Uint64;\r
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
\r
+\r
+/**\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved3:17;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r
+\r
#endif\r
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