returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
+/**\r
+ Is Intel(R) Core(TM) 2 Processor Family?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x0F || \\r
+ DisplayModel == 0x17 \\r
+ ) \\r
+ )\r
+\r
/**\r
Shared. Model Specific Platform ID (R).\r
\r
UINT32 Reserved2:19;\r
UINT32 Reserved3:18;\r
///\r
- /// [Bits 52:50] See Table 35-2.\r
+ /// [Bits 52:50] See Table 2-2.\r
///\r
UINT32 PlatformId:3;\r
UINT32 Reserved4:11;\r
\r
\r
/**\r
- Unique. Control Features in Intel 64Processor (R/W) See Table 35-2.\r
+ Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.\r
\r
@param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)\r
@param EAX Lower 32-bits of MSR value.\r
\r
/**\r
Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the source instruction for one of the last four\r
- branches, exceptions, or interrupts taken by the processor. See also: -\r
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,\r
- Interrupt, and Exception Recording (Pentium M Processors).".\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction. See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.5.\r
\r
@param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP\r
@param EAX Lower 32-bits of MSR value.\r
\r
/**\r
Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction for one of the last four\r
- branches, exceptions, or interrupts taken by the processor.\r
+ record registers on the last branch record stack. This To_IP part of the\r
+ stack contains pointers to the destination instruction.\r
\r
@param ECX MSR_CORE2_LASTBRANCH_n_TO_IP\r
@param EAX Lower 32-bits of MSR value.\r
UINT64 Uint64;\r
} MSR_CORE2_FSB_FREQ_REGISTER;\r
\r
-\r
-/**\r
- Shared.\r
-\r
- @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_BBL_CR_CTL3_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);\r
- AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
-**/\r
-#define MSR_CORE2_BBL_CR_CTL3 0x0000011E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
- /// Indicates if the L2 is hardware-disabled.\r
- ///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
- /// Disabled (default) Until this bit is set the processor will not\r
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
- ///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved2:14;\r
- ///\r
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
- ///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved3:8;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_BBL_CR_CTL3_REGISTER;\r
-\r
-\r
/**\r
Shared.\r
\r
///\r
struct {\r
///\r
- /// [Bit 0] Fast-Strings Enable See Table 35-2.\r
+ /// [Bit 0] Fast-Strings Enable See Table 2-2.\r
///\r
UINT32 FastStrings:1;\r
UINT32 Reserved1:2;\r
///\r
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 35-2.\r
+ /// Table 2-2.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.\r
+ /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
///\r
UINT32 PerformanceMonitoring:1;\r
UINT32 Reserved3:1;\r
///\r
UINT32 FERR:1;\r
///\r
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
+ /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See\r
- /// Table 35-2.\r
+ /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
+ /// Table 2-2.\r
///\r
UINT32 PEBS:1;\r
///\r
UINT32 Reserved4:2;\r
///\r
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 35-2.\r
+ /// Table 2-2.\r
///\r
UINT32 EIST:1;\r
UINT32 Reserved5:1;\r
///\r
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
+ /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
UINT32 MONITOR:1;\r
///\r
UINT32 EISTLock:1;\r
UINT32 Reserved6:1;\r
///\r
- /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2.\r
+ /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
///\r
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
UINT32 xTPR_Message_Disable:1;\r
UINT32 Reserved7:8;\r
UINT32 Reserved8:2;\r
///\r
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.\r
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
///\r
UINT32 XD:1;\r
UINT32 Reserved9:2;\r
///\r
struct {\r
///\r
- /// [Bits 5:0] LBR Format. See Table 35-2.\r
+ /// [Bits 5:0] LBR Format. See Table 2-2.\r
///\r
UINT32 LBR_FMT:6;\r
///\r
///\r
UINT32 PEBS_FMT:1;\r
///\r
- /// [Bit 7] PEBSSaveArchRegs. See Table 35-2.\r
+ /// [Bit 7] PEBSSaveArchRegs. See Table 2-2.\r
///\r
UINT32 PEBS_ARCH_REG:1;\r
UINT32 Reserved1:24;\r
\r
\r
/**\r
- Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
- Facilities.".\r
+ Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
\r
- @param ECX MSR_CORE2_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);\r
@endcode\r
- @note MSR_CORE2_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
+ @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_CORE2_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
+#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r
\r
\r
/**\r
- Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r
-\r
- @param ECX MSR_CORE2_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.\r
-**/\r
-#define MSR_CORE2_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
-/**\r
- Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r
+ Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
\r
@param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r
+ Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
\r
@param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling\r
+ Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
(PEBS).".\r
\r
@param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)\r
} MSR_CORE2_PEBS_ENABLE_REGISTER;\r
\r
\r
-/**\r
- Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_CORE2_MC4_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
-**/\r
-#define MSR_CORE2_MC4_CTL 0x0000040C\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_CORE2_MC4_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_MC4_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC4_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_CORE2_MC4_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
-**/\r
-#define MSR_CORE2_MC4_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_CORE2_MC3_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
-**/\r
-#define MSR_CORE2_MC3_CTL 0x00000410\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_CORE2_MC3_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_MC3_STATUS 0x00000411\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC3_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_CORE2_MC3_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
-**/\r
-#define MSR_CORE2_MC3_ADDR 0x00000412\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC3_MISC (0x00000413)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r
-**/\r
-#define MSR_CORE2_MC3_MISC 0x00000413\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_CTL (0x00000414)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
-**/\r
-#define MSR_CORE2_MC5_CTL 0x00000414\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_STATUS (0x00000415)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_MC5_STATUS 0x00000415\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_ADDR (0x00000416)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
-**/\r
-#define MSR_CORE2_MC5_ADDR 0x00000416\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_MISC (0x00000417)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
-**/\r
-#define MSR_CORE2_MC5_MISC 0x00000417\r
-\r
-\r
-/**\r
- Unique. Apply to Intel Xeon processor 7400 series (processor signature\r
- 06_1D) only. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS." and Chapter 23.\r
-\r
- @param ECX MSR_CORE2_MC6_STATUS (0x00000419)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_MC6_STATUS 0x00000419\r
-\r
-\r
/**\r
Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon\r
processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
projects / mirror_edk2.git / blobdiff